UM0306 Controller area network (bxCAN)
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Bits 31:16 Reserved, forced by hardware to 0.
Bit 16
DBF: (non user) - Debug Freeze (ENFCT)
0: CAN working during debug break activated
1: CAN reception/transmission frozen during debug. Reception FIFOs can still be
accessed/controlled normally.
Bit 15
RESET: bxCAN software master reset
0: Normal operation.
1: Force a master reset of the bxCAN -> SLEEP mode activated after reset (FMP
bits and CAN_MCR register are initialized to the reset values). This bit is
automatically reset to 0.
Bits 14:8 Reserved, forced by hardware to 0.
Bits 31:8 Reserved, forced by hardware to 0.
Bit 7
TTCM: Time Triggered Communication Mode
0: Time Triggered Communication mode disabled.
1: Time Triggered Communication mode enabled
Note: For more information on Time Triggered Communication mode, please refer to
Section 14.5.2: Time triggered communication mode.
Bit 6
ABOM: Automatic Bus-Off Management
This bit controls the behavior of the CAN hardware on leaving the Bus-Off state.
0: The Bus-Off state is left on software request, once 128 occurrences of 11
recessive bits have been monitored and the software has first set and cleared the
INRQ bit of the CAN_MCR register.
1: The Bus-Off state is left automatically by hardware once 128 occurrences of 11
recessive bits have been monitored.
For detailed information on the Bus-Off state please refer to Section 14.5.6: Error
management.
Bit 5
AWUM: Automatic Wake-Up Mode
This bit controls the behavior of the CAN hardware on message reception during
SLEEP mode.
0: The SLEEP mode is left on software request by clearing the SLEEP bit of the
CAN_MCR register.
1: The SLEEP mode is left automatically by hardware on CAN message detection.
The SLEEP bit of the CAN_MCR register and the SLAK bit of the CAN_MSR
register are cleared by hardware.
Bit 4
NART: No Automatic Retransmission
0: The CAN hardware will automatically retransmit the message until it has been
successfully transmitted according to the CAN standard.
1: A message will be transmitted only once, independently of the transmission
result (successful, error or arbitration lost).
Bit 3
RFLM: Receive FIFO Locked Mode
0: Receive FIFO not locked on overrun. Once a receive FIFO is full the next
incoming message will overwrite the previous one.
1: Receive FIFO locked against overrun. Once a receive FIFO is full the next
incoming message will be discarded.
Bit 2
TXFP: Transmit FIFO Priority
This bit controls the transmission order when several mailboxes are pending at the
same time.
0: Priority driven by the identifier of the message
1: Priority driven by the request order (chronologically)
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