Controller area network (bxCAN) UM0306
318/519
Receive FIFO mailbox data length control and time stamp register
(CAN_RDTxR) (x=0..1)
Address Offsets: 1B4h, 1C4h
Reset Value: xxh
Note: All RX registers are write protected.
Receive FIFO mailbox data low register (CAN_RDLxR) (x=0..1)
All bits of this register are write protected when the mailbox is not in empty state.
Address Offsets: 1B8h, 1C8h
Reset Value: xxh
Note: All RX registers are write protected.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIME[15:0]
rrrrrrrrrrrrrrrr
1514131211109876543210
FMI[7:0] Reserved DLC[3:0]
rrrrrrrr rrrr
Bits 31:16
TIME[15:0]: Message Time Stamp
This field contains the 16-bit timer value captured at the SOF detection.
Bits 15:8
FMI[7:0]: Filter Match Index
This register contains the index of the filter the message stored in the mailbox
passed through. For more details on identifier filtering please refer to
Section 14.5.4: Identifier filtering on page 291 - Filter Match Index paragraph.
Bits 7:4 Reserved, forced by hardware to 0.
Bits 3:0
DLC[3:0]: Data Length Code
This field defines the number of data bytes a data frame contains (0 to 8). It is 0 in
the case of a remote frame request.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA3[7:0] DATA2[7:0]
rrrrrrrrrrrrrrrr
1514131211109876543210
DATA1[7:0] DATA0[7:0]
rrrrrrrrrrrrrrrr
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