UM0306 Inter-integrated circuit (I2C) interface
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The master can decide to enter Transmitter or Receiver mode depending on the LSB of the
slave address sent.
● In 7-bit addressing mode,
– To enter Transmitter mode, a master sends the slave address with LSB reset.
– To enter Receiver mode, a master sends the slave address with LSB set.
● In 10-bit addressing mode,
– To enter Transmitter mode, a master sends the header (11110xx0) and then the
slave address with LSB reset, (where xx denotes the two most significant bits of
the address).
– To enter Receiver mode, a master sends the header (11110xx0) and then the
slave address with LSB reset. Then it should send a repeated Start condition
followed by the header (11110xx1), (where xx denotes the two most significant bits
of the address).
The TRA bit indicates whether the master is in Receiver or Transmitter mode.
Master transmitter
Following the address transmission and after clearing ADDR, the master sends bytes from
the DR register to the SDA line via the internal shift register.
The master waits until TxE is cleared, (see Figure 137 Transfer sequencing EV8).
When the acknowledge pulse is received:
● The TxE bit is set by hardware and an interrupt is generated if the ITEVFEN and
ITBUFEN bits are set.
If TxE is set and a data byte was not written in the DR register before the end of the last data
transmission, BTF is set and the interface waits until BTF is cleared.
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