Inter-integrated circuit (I2C) interface UM0306
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Bit 15
SWRST: Software Reset
When set, the I2C is under reset state. Before resetting this bit, make sure the
I2C lines are released and the bus is free.
0: I
2
C Peripheral not under reset
1: I
2
C Peripheral under reset state
Note:
This bit can be used in case the BUSY bit is set to ‘1’ when no stop condition has
been detected on the bus.
Bit 14 Reserved, forced by hardware to 0.
Bit 13
ALERT: SMBus Alert
This bit is set and cleared by software, and cleared by hardware when PE=0.
0: Releases SMBAlert pin high. Alert Response Address Header followed by
NACK.
1: Drives SMBAlert pin low. Alert Response Address Header followed by ACK.
Bit 12
PEC: Packet Error Checking.
This bit is set and cleared by software, and cleared by hardware when PEC is
transferred or by a START or STOP condition or when PE=0.
0: No PEC transfer
1: PEC transfer (in Tx or Rx mode)
Note: PEC calculation is corrupted by an arbitration loss.
Bit 11
POS: Acknowledge/PEC Position (for data reception).
This bit is set and cleared by software and cleared by hardware when PE=0.
0: ACK bit controls the (N)ACK of the current byte being received in the shift
register. The PEC bit indicates that current byte in shift register is a PEC.
1: ACK bit controls the (N)ACK of the next byte which will be received in the shift
register. The PEC bit indicates that the next byte in the shift register is a PEC
Note:
This bit must be configured before data reception starts.
This configuration must be used only in ADDR stretch event in case there are only
2 data bytes
Bit 10
ACK: Acknowledge Enable
This bit is set and cleared by software and cleared by hardware when PE=0.
0: No acknowledge returned
1: Acknowledge returned after a byte is received (matched address or data)
Bit 9
STOP: Stop Generation
The bit is set and cleared by software, cleared by hardware when a Stop
condition is detected, set by hardware when a timeout error is detected.
In Master Mode:
0: No Stop generation.
1: Stop generation after the current byte transfer or after the current Start
condition is sent.
In Slave mode:
0: No Stop generation.
1: Release the SCL and SDA lines after the current byte transfer.
Note:
In Master mode, the BTF bit of the I2C_SR1 register must be cleared when
STOP is requested.
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