ST STM32F10 Series User Manual

Inter-integrated circuit (I2C) interface UM0306
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15.6.2 Control register 2 (I2C_CR2)
Address offset: 04h
Reset Value: 0000h
15141312111098 7 6543210
Reserved LAST
DMA
EN
ITBUF
EN
ITEVT
EN
ITER
REN
Reserved FREQ[5:0]
rw rw rw rw rw rw rw rw rw rw rw
Bits 15:13 Reserved, forced by hardware to 0.
Bit 12
LAST: DMA Last Transfer
0: Next DMA EOT is not the last transfer
1: Next DMA EOT is the last transfer
Note:
This bit is used in master receiver mode to permit the generation of a NACK on the
last received data.
Bit 11
DMAEN: DMA Requests Enable
0: DMA requests disabled
1: DMA request enabled when TxE=1 or RxNE =1
Note: The DMAEN bit must be set only after receiving the address sequence,
when ADDR is cleared.
Bit 10
ITBUFEN: Buffer Interrupt Enable
0: TxE = 1 or RxNE = 1 does not generate any interrupt.
1:TxE = 1 or RxNE = 1 generates Event Interrupt (whatever the state of
DMAEN)
Bit 9
ITEVTEN: Event Interrupt Enable
0: Event interrupt disabled
1: Event interrupt enabled
This interrupt is generated when:
– SB = 1 (Master)
– ADDR = 1 (Master/Slave)
– ADD10= 1 (Master)
–STOPF = 1 (Slave)
– BTF = 1 with no TxE or RxNE event
– TxE event to 1 if ITBUFEN = 1
– RxNE event to 1if ITBUFEN = 1
Bit 8
ITERREN: Error Interrupt Enable
0: Error interrupt disabled
1: Error interrupt enabled
This interrupt is generated when:
– BERR = 1
–ARLO = 1
–AF = 1
–OVR = 1
– PECERR = 1
–TIMEOUT = 1
– SMBAlert = 1
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ST STM32F10 Series Specifications

General

Brand	ST
Model	STM32F10 Series
Category	Microcontrollers
Language	English