Serial peripheral interface (SPI) UM0306
370/519
Bit 12
CRCNEXT: Transmit CRC next
0: Next transmit value is from Tx buffer
1: Next transmit value is from Tx CRC register
Notes:
This bit has to be written as soon as the last data is written into the SPI_DR
register.
This bit is only used in full-duplex mode.
Bit 11
DFF: Data Frame Format
0: 8-bit data frame format is selected for transmission/reception
1: 16-bit data frame format is selected for transmission/reception
Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for
correct operation
Bit 10
RXONLY: Receive only
This bit combined with BIDImode bit selects the direction of transfer in 2 line
uni-directional mode. This bit is also useful in a multi-slave system in which
this particular slave is not accessed, the output from the accessed slave is
not corrupted.
0: Full duplex (Transmit and receive)
1: Output disabled (Receive only mode)
Bit 9
SSM: Software slave management
When the SSM bit is set, the NSS pin input is replaced with the value from
the SSI bit.
0: Software slave management disabled
1: Software slave management enabled
Bit 8
SSI: Internal slave select
This bit has effect only when SSM bit is set. The value of this bit is forced
onto the NSS pin and the I/O value of the NSS pin is ignored.
Bit 7
LSBFIRST: Frame Format
0: MSB transmitted first
1: LSB transmitted first
Note: This bit should not be changed when the communication is ongoing.
Bit 6
SPE: SPI Enable
0: Peripheral disabled
1: Peripheral enabled
Bits 5:3
BR[2:0]: Baud Rate Control
000: f
CPU
/2
001: f
CPU
/4
010: f
CPU
/8
011: f
CPU
/16
100: f
CPU
/32
101: f
CPU
/64
110: f
CPU
/128
111: f
CPU
/256
Note: These bits should not be changed when the communication is ongoing.
Bit 2
MSTR: Master Selection
0: Slave configuration
1: Master configuration
Note: This bit should not be changed when the communication is ongoing.
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