UM0306 USB full speed device interface (USB)
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As a first step application software needs to activate register macrocell clock and de-assert
macrocell specific reset signal using related control bits provided by device clock
management logic.
After that the analog part of the device related to the USB transceiver must be switched on
using the PDWN bit in CNTR register which requires a special handling. This bit is intended
to switch on the internal voltage references supplying the port transceiver. Since this circuits
have a defined startup time, during which the behavior of USB transceiver is not defined, it is
necessary to wait this time, after having set the PDWN bit in CNTR register, then the reset
condition on the USB part can be removed (clearing of FRES bit in CNTR register) and the
ISTR register can be cleared, removing any spurious pending interrupt, before enabling any
other macrocell operation.
As a last step the USB specific 48 MHz clock needs to be activated, using the related
control bits provided by device clock management logic.
At system reset, the microcontroller must initialize all required registers and the packet
buffer description table, to make the USB Peripheral able to properly generate interrupts and
data transfers. All registers not specific to any endpoint must be initialized according to the
needs of application software (choice of enabled interrupts, chosen address of packet
buffers, etc.). Then the process continues as for the USB reset case (see further
paragraph).
USB reset (RESET interrupt)
When this event occurs, the USB Peripheral is put in the same conditions it is left by the
system reset after the initialization described in the previous paragraph: communication is
disabled in all endpoint registers (the USB Peripheral will not respond to any packet). As a
response to the USB reset event, USB function must be enabled, having as USB address 0,
implementing only the default control endpoint (endpoint address is 0 too). This is
accomplished by setting the Enable Function (EF) bit of the register and initializing the
EP0R register and its related packet buffers accordingly. During USB enumeration process,
the host assigns a unique address to this device, which must be written in the ADD[6:0] bits
of the register, and configures any other necessary endpoint.
When a RESET interrupt is received, the application software is responsible to enable again
the default endpoint of USB function 0 within 10mS from the end of reset sequence which
triggered the interrupt.
Structure and usage of packet buffers
Each bidirectional endpoint may receive or transmit data from/to the host. The received data
is stored in a dedicated memory buffer reserved for that endpoint, while another memory
buffer contains the data to be transmitted by the endpoint. Access to this memory is
performed by the packet buffer interface block, which delivers a memory access request and
waits for its acknowledgement. Since the packet buffer memory has to be accessed by the
microcontroller also, an arbitration logic takes care of the access conflicts, using half APB1
cycle for microcontroller access and the remaining half for the USB Peripheral access. In
this way, both the agents can operate as if the packet memory is a dual-port SRAM, without
being aware of any conflict even when the microcontroller is performing back-to-back
accesses. The USB Peripheral logic uses a dedicated clock. The frequency of this dedicated
clock is fixed by the requirements of the USB standard at 48 MHz, and this can be different
from the clock used for the interface to the APB1 bus. Different clock configurations are
possible where the APB1 clock frequency can be higher or lower than the USB Peripheral
one.
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