EasyManuals Logo

ST STM32F10 Series User Manual

ST STM32F10 Series
519 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #434 background imageLoading...
Page #434 background image
USB full speed device interface (USB) UM0306
434/519
completed by the host PC and its end can be monitored again using the RXDP and RXDM
bits in the register.
Note: The RESUME bit must be anyway used only after the USB Peripheral has been put in
suspend mode, setting the FSUSP bit in register to 1.
18.6 USB register description
The USB Peripheral registers can be divided into the following groups:
Common Registers: Interrupt and Control registers
Endpoint Registers: Endpoint configuration and status
Buffer Descriptor Table: Location of packet memory used to locate data buffers
All register addresses are expressed as offsets with respect to the USB Peripheral registers
base address 0xC000 8000, except the buffer descriptor table locations, which starts at the
address specified by the register. Due to the common limitation of APB1 bridges on word
addressability, all register addresses are aligned to 32-bit word boundaries although they
are 16-bit wide. The same address alignment is used to access packet buffer memory
locations, which are located starting from 0xC000 8800.
Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions.
18.6.1 Common registers
These registers affect the general behavior of the USB Peripheral defining operating mode,
interrupt handling, device address and giving access to the current frame number updated
by the host PC.
USB control register ()
Address Offset: 40h
Reset Value: 0000 0000 0000 0011b (0003h)
1514131211109876543210
rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit 15
CTRM: Correct Transfer Interrupt Mask
0: Correct Transfer (CTR) Interrupt disabled.
1: CTR Interrupt enabled, an interrupt request is generated when the corresponding
bit in the register is set.
Bit 14
PMAOVRM: Packet Memory Area Over / Underrun Interrupt Mask
0: PMAOVR Interrupt disabled.
1: PMAOVR Interrupt enabled, an interrupt request is generated when the
corresponding bit in the register is set.
Bit 13
ERRM: Error Interrupt Mask
0: ERR Interrupt disabled.
1: ERR Interrupt enabled, an interrupt request is generated when the corresponding
bit in the register is set.
www.BDTIC.com/ST

Table of Contents

Other manuals for ST STM32F10 Series

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the ST STM32F10 Series and is the answer not in the manual?

ST STM32F10 Series Specifications

General IconGeneral
BrandST
ModelSTM32F10 Series
CategoryMicrocontrollers
LanguageEnglish

Related product manuals