Debug support (DBG) UM0306
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The ARM Cortex-M3 core provides integrated on-chip debug support. It is comprised of:
● SWJ-DP: Serial wire / JTAG debug port
● AHP-AP: AHB access port
● ITM: Instrumentation trace macrocell
● FPB: Flash patch breakpoint
● DWT: Data watchpoint trigger
● TPUI: Trace port unit interface (available on larger packages, where the corresponding
pins are mapped)
It also includes debug features dedicated to STM32F10x:
● Flexible debug pinout assignment
● MCU debug box (support for low-power modes, control over peripheral clocks, etc.)
Note: For further information on debug functionality supported by the ARM Cortex-M3 core, refer
to the Cortex-M3 r1p1 Technical Reference Manual (TRM) and to the CoreSight Design Kit
r1p0 TRM.
20.2 Referenced ARM documentation
●
Cortex-M3 r1p1 Technical Reference Manual (TRM)
●
ARM Debug Interface V5
●
ARM CoreSight Design Kit revision r1p0 Technical Reference Manual
20.3 SWJ debug port (serial wire and JTAG)
The STM32F10x core integrates the Serial Wire / JTAG Debug Port (SWJ-DP). It is an ARM
standard CoreSight debug port that combines a JTAG-DP (5-pin) interface and a SW-DP (2-
pin) interface.
● The JTAG Debug Port (JTAG-DP) provides a 5-pin standard JTAG interface to the AHP-
AP port.
● The Serial Wire Debug Port (SW-DP) provides a 2-pin (clock + data) interface to the
AHP-AP port.
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