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General| Brand | AMCC |
|---|---|
| Model | PPC405 |
| Category | Computer Hardware |
| Language | English |
Highlights key features like five-stage pipeline, unaligned load/store support, 32 GPRs, static branch prediction, hardware multiply/divide.
Explains the organization of the processor core, including pipeline, cache units, MMU, debug, and interfaces.
Explains the two operating modes: privileged (supervisor) for full access, and user (problem) for restricted access.
Describes the 32-bit effective address space and translation to 36-bit real addresses via MMU.
Details the thirty-two 32-bit GPRs used for data transfer and as operands in integer instructions.
Categorizes and describes SPRs used for debug, timers, interrupts, storage control, and other processor resources.
Details the 32-bit CR, grouped into eight 4-bit fields, used for logical operations and branch control.
Details the MSR, a 32-bit register controlling processor core functions like interrupts and address translation.
Lists ICU features: programmable pipelining, non-cacheable hits, bypass path, and cache control instructions.
Details DCU features: pipelining, load/store hits, write-back/write-through strategies, and PLB slaves.
Details the MMU's functions: address translation, protection, and support for virtual memory.
Explains how MSR fields control MMU usage for address translation and the process of EA to real address translation.
Describes the TLB hardware for controlling translation, protection, and storage attributes.
Details the unified TLB (UTLB) containing 64 entries, each with TLBHI (tag) and TLBLO (data) portions.
Categorizes TLB entry fields: page identification, control, access, and storage attributes.
Covers virtual-mode access protection, controlling general access, write, and execute permissions via TLB entries.
Details interrupt priorities, masking mechanisms, and how simultaneous interrupts are handled.
Categorizes interrupts as noncritical (data storage, instruction storage, etc.) and critical (machine checks, debug).
Lists general interrupt handling registers: MSR, SRR0–SRR3, EVPR, ESR, and DEAR.
Covers machine check interrupts occurring due to hardware or storage subsystem failures, or invalid addresses.
Describes data storage interrupts for disallowed access to EA, including U0 faults and zone faults.
Details instruction storage interrupts for disallowed fetch access, including zone faults and guarded regions.
Explains supported debug modes: internal, external, debug wait, and real-time trace.
Lists debug functions for processor control: step, stuff, halt, stop, reset, debug events, freeze timers, trap instructions.
Lists debug registers (DBCR0, DBCR1, DBSR) not intended for application code use.
Details debug control registers (DBCR0, DBCR1) for enabling/configuring debug events and setting processor mode.
Describes the DBSR containing status on debug events and most recent reset; status bits are normally set by events or resets.
Lists debug events (enabled by DBCR0/1, recorded in DBSR) that trigger debug operations.
Lists all available PPC405 instructions alphabetically, including extended mnemonics.
Details the 32 GPRs, their contents, and how they are addressed by load/store and integer instructions.
Describes MSR and CR access via special instructions, not requiring addressing.
Lists SPRs, their mnemonics, names, SPR numbers, and access modes.
Contains PPC405 instructions summarized alphabetically and by opcode.
Lists all PPC405 mnemonics, including extended mnemonics, alphabetically.
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