AMCC PPC405 - Alignment and Endian Operation; Alignment for Storage Reference and Cache Control Instructions; Summary of Instructions Causing Alignment Exceptions; Table 2-5. Alignment Exception Summary

AMCC Proprietary 43
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
2.4.1 Alignment for Storage Reference and Cache Control Instructions
The storage reference instructions (loads and stores; see Table 2-14) move data to and from storage. The data
cache control instructions listed in Table 2-23, control the contents and operation of the data cache unit (DCU).
Both types of instructions form an effective address (EA). The method of calculating the EA for the storage
reference and cache control instructions is detailed in the description of those instructions. See Instruction Set on
page 157 for more information.
Cache control instructions ignore the five least significant bits of the EA; no alignment restrictions exist in the DCU
because of EAs. However, storage control attributes can cause alignment exceptions. When data address
translation is disabled and a dcbz instruction references a storage region that is non cacheable, or for which write-
through caching is the write strategy, an alignment exception is taken. Such exceptions result from the storage
control attributes, not from EA alignment.
The alignment exception enables system software to emulate the write-through function. Alignment requirements
for the storage reference instructions and the dcread instruction depend on the particular instruction. Table 2-5,
summarizes the instructions that cause alignment exceptions.
The data targets of instructions are of types that depend upon the instruction. The load/store instructions have the
following “natural” alignments:
• Load/store word instructions have word targets, word-aligned.
• Load/ store halfword instructions have halfword targets, halfword-aligned.
• Load/store byte instructions have byte targets, byte-aligned (that is, any alignment).
Misalignments are addresses that are not naturally aligned on data type boundaries. An address not divisible by
four is misaligned with respect to word instructions. An address not divisible by two is misaligned with respect to
halfword instructions. The PPC405 implementation handles misalignments within and across word boundaries, but
there is a performance penalty because additional cycles are required.
2.4.2 Alignment and Endian Operation
The endian storage control attribute does not affect alignment behavior. In little endian storage regions, the
alignment of data is treated as it is in big endian storage regions; no special alignment exceptions occur when
accessing data in little endian storage regions. Note that the alignment exceptions that apply to big endian region
accesses also apply to little endian storage region accesses.
2.4.3 Summary of Instructions Causing Alignment Exceptions
Table 2-5 summarizes the instructions that cause alignment exceptions and the conditions under which the
alignment exceptions occur.
Table 2-5. Alignment Exception Summary
Instructions Causing Alignment Exceptions Conditions
dcbz
EA in non cacheable or write-through storage
dcread, lwarx, stwcx. EA not word-aligned