AMCC Proprietary 81
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
3.6.3 DCU Debugging
The
dcread instruction provides a debugging tool for reading the data cache entries for the congruence class
specified by EA18:26. The cache information is read into a GPR.
If CCR0[CIS] = 0, the data is a word of DCU data from the addressed line, specified by EA27:29. If EA30:31 are not
00, an alignment exception occurs. If CCR0[CWS] = 0, the data is from the A-way; otherwise; the data is from the
B-way.
If CCR0[CIS] = 1, the cache information is the cache tag. If CCR0[CWS] = 0, the tag is from the Away; otherwise
the tag is from the B-way.
DCU tag information is placed into bits 0:19 of a GPR.
Note: A “dirty” cache line is one which has been accessed by a store instruction after it was established, and can
be inconsistent with external memory.
3.7 DCU Performance
DCU performance depends upon the application, but, in general, cache hits complete in one cycle without stalling
the CPU pipeline. Under certain conditions and limitations of the DCU, the pipeline stalls (stops executing
instructions) until the DCU completes current operations.
Several factors affect DCU performance, including:
• Pipeline stalls
• DCU priority
• Simultaneous cache operations
• Sequential cache operations
3.7.1 Pipeline Stalls
The CPU issues commands for cache operations to the DCU. If the DCU can immediately perform the requested
cache operation, no pipeline stall occurs. In some cases, however, the DCU cannot immediately perform the
requested cache operation, and the pipeline stalls until the DCU can perform the pending cache operation.
In general, the DCU, when hitting in the cache array, can execute a load/store every cycle. If a cache miss occurs,
the DCU must retrieve the line from main memory. For cache misses, the DCU stores the cache line in a line fill
buffer until the entire cache line is received. The DCU can accept new DCU commands while the fill progresses. If
the instruction causing the line fill is a load, the target word is bypassed to the GPR during the cycle after it
becomes available in the fill buffer. When the fill buffer is full, it must be moved into the tag and data arrays. During
this time, the DCU cannot begin a new cache operation and stalls the pipeline if new DCU commands are
presented. Storing a line in the line fill buffer takes three cycles, unless the line being replaced has been modified.
In that case, the operation takes four cycles.
The DCU can accept up to two load commands. If the data for the first load command is not immediately available,
the DCU can still accept the second load command. If the load data is not required by subsequent instructions,
those instructions will continue to execute. If data is required from either load command, the CPU pipeline will stall
until the load data has been delivered. The pipeline will also stall until the second load has read the data array if a
subsequent data cache command is issued.
In general, if the fill buffer is being used and the next load or store command requires the fill buffer, only one
additional command can be accepted before causing additional DCU commands to stall the pipeline.
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