AMCC PPC405 - Table 9-12. Extended Mnemonics for Cmpl

AMCC Proprietary 190
Revision 1.02 - September 10, 2007
PPC405 Processor
cmpl
Compare Logical
Preliminary User’s Manual
cmpl
Compare Logical
c
0:3
←
4
0
if (RA) (RB) then c
0
← 1
if (RA) (RB) then c
1
← 1
if (RA) (RB) then c
2
← 1
c
3
← XER[SO]
n
← BF
CR[CRn] ← c
0:3
The contents of register RA are compared with the contents of register RB, using a 32-bit unsigned compare.
The CR field specified by the BF field is updated to reflect the results of the compare and the value of XER[SO] is
placed into the same CR field.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
• CR[CRn] where n is specified by the BF field
Invalid Instruction Forms
• Reserved fields
Programming Notes
The PowerPC Architecture defines this instruction as cmpl BF,L,RA,RB, where L selects operand size for 64-bit
PowerPC implementations. For all 32-bit PowerPC implementations, L = 0 is required (L = 1 is an invalid form);
hence for PPC405, use of the extended mnemonic cmplw BF,RA,RB is recommended.
Architecture Note
This instruction is part of the PowerPC User Instruction Set Architecture.
cmpl BF, 0, RA, RB
31 BF
RA RB 32
069111621 31
Table 9-12. Extended Mnemonics for cmpl
Mnemonic Operands Function
Other Registers
Altered
cmplw [BF,] RA, RB
Compare Logical Word.
Use CR0 if BF is omitted.
Extended mnemonic for
cmpl BF,0,RA,RB
<
u
>
u
=