AMCC PPC405 - OCM Registers

88 AMCC Proprietary
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
Examples 5 and 6 bypass data out of the store data queue because the aliased addresses compare within a 16KB
address space. In both examples, address bits 18:29 match, and load data is returned from the store data queue.
4.3 OCM Registers
The OCM controller uses Device Control Registers (DCRs) to store or access data in the OCM. DCRs are unique
to the chip in which this processor is instantiated and are not a part of the processor. Refer to the appropriate chip
user’s manual for details on the DCRs.