134 AMCC Proprietary
Revision 1.01 - February 19, 2007
PPC405 Processor
Preliminary User’s Manual
The controls described in Figure 7-4 imply three different modes of using the watchdog timer. The modes assume
that TCR[WRC] was set to allow processor reset by the watchdog timer:
1. Always take a pending watchdog interrupt, and never attempt to prevent its occurrence. (This mode is
described in the preceding text.)
a. Clear TSR[WIS] in the watchdog timer handler.
b. Never use TSR[ENW].
2. Always take a pending watchdog interrupt, but avoid it whenever possible by delaying a reset until a second
watchdog timer occurs.
This assumes that a recurring code loop of known maximum duration exists outside the interrupt handlers, or
that a FIT interrupt handler is operational. One of these mechanisms clears TSR[ENW] more frequently than
the watchdog period.
a. Clear TSR[ENW] to 0 in loop or in FIT interrupt handler.
To clear TSR[ENW], use mtspr to write a 1 to TSR[ENW] (and to any other bits that are to be cleared), with
0 in all other bit locations.
b. Clear TSR[WIS] in watchdog timer handler.
It is not expected that a watchdog interrupt will occur every time, but only if an exceptionally high execution
load delays clearing of TSR[ENW] in the usual time frame.
3. Never take a watchdog interrupt.
This assumes that a recurring code loop of reliable duration exists outside the interrupt handlers, or that a FIT
interrupt handler is operational. This method only guarantees one watchdog timeout period before a reset
occurs.
a. Clear TSR[WIS] in the loop or in FIT handler.
b. Never use TSR[ENW] but have it set.
Table 7-4. Watchdog Timer State Machine
Enable Next Watchdog
TSR[ENW]
Watchdog Timer
Status
TSR[WIS]
Action When Timer Interval Expires
0 0 Set TSR[ENW] = 1.
0 1 Set TSR[ENW] = 1.
10
Set TSR[WIS] = 1.
If TCR[WIE] = 1 and MSR[CE] = 1, then interrupt.
11
Cause the watchdog reset action specified by TCR[WRC].
On reset, copy current TCR[WRC] to TSR[WRS] and clear TCR[WRC], disabling the
watchdog timer.
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