AMCC PPC405 - 6.5 General Interrupt Handling Registers

114 AMCC Proprietary
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
6.5 General Interrupt Handling Registers
The general interrupt handling registers are the Machine State Register (MSR), SRR0–SRR3, the Exception
Vector Prefix Register (EVPR), the Exception Syndrome Register (ESR), and the Data Exception Address Register
(DEAR).
6.5.1 Machine State Register (MSR)
The MSR is a 32-bit register that holds the current context of the PPC405. When a noncritical interrupt is taken, the
MSR contents are written to SRR1; when a critical interrupt is taken, the MSR contents are written to SRR3. When
an rfi or rfci instruction executes, the contents of the MSR are read from SRR1 or SRR3, respectively.
Programming Note: The rfi and rfci instructions can alter reserved MSR fields.
The MSR contents can be read into a General Purpose Register (GPR) using an mfmsr instruction. The contents
of a GPR can be written to the MSR using an mtmsr instruction. The MSR[EE] bit may be set/cleared atomically
using the wrtee or wrteei instructions.
Figure 6-1. Machine State Register (MSR)
0:12
Reserved
13 WE Wait State Enable
0 The processor is not in the wait state.
1 The processor is in the wait state.
If MSR[WE] = 1, the processor remains in the wait
state until an interrupt is taken, a reset occurs, or
an external debug tool clears WE.
14 CE Critical Interrupt Enable
0 Critical interrupts are disabled.
1 Critical interrupts are enabled.
Controls the critical interrupt input and watchdog
timer first time-out interrupts.
15
Reserved
16 EE External Interrupt Enable
0 Asynchronous interrupts (external to the
processor core) are disabled.
1 Asynchronous interrupts are enabled.
Controls the non-critical external interrupt input,
PIT, and FIT interrupts.
17 PR Problem State
0 Supervisor state (all instructions allowed).
1 Problem state (some instructions not allowed).
18
Reserved
19 ME Machine Check Enable
0 Machine check interrupts are disabled.
1 Machine check interrupts are enabled.
20
Reserved
21 DWE Debug Wait Enable
0 Debug wait mode is disabled.
1 Debug wait mode is enabled.
22 DE Debug Interrupts Enable
0 Debug interrupts are disabled.
1 Debug interrupts are enabled.
23:25
Reserved
26 IR Instruction Relocate
0 Instruction address translation is disabled.
1 Instruction address translation is enabled.