74 AMCC Proprietary
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
Cache lines are always completely flushed or filled, even if the program does not request the rest of the bytes in
the line, or if a bus error occurs after a bus interface unit accepts the request for the line fill. If a bus error occurs
during a line fill, the line is filled and the data is marked valid. However, the line can contain invalid data, and a
machine check exception occurs.
3.4.2 DCU Write Strategies
DCU operations can use write-back or write-through strategies to maintain coherency with external cacheable
memory.
The write-back strategy updates only the data cache, not external memory, during store operations. Only modified
data lines are flushed to external memory, and then only when necessary to free up locations for incoming lines, or
when lines are explicitly flushed using dcbf or dcbst instructions. The write-back strategy minimizes the amount of
external bus activity and avoids unnecessary contention for the external bus between the ICU and the DCU.
The write-back strategy is contrasted with the write-through strategy, in which stores are written simultaneously to
the cache and to external memory. A write-through strategy can simplify maintaining coherency between cache
and memory.
When data address translation is enabled (MSR[DR] = 1), the W storage attribute in the TLB entry for the memory
page controls the write strategy for the page. If TLB_entry[W] = 0, write-back is selected; otherwise, write-through
is selected. The write strategy is controlled separately for each page. Translation Lookaside Buffer (TLB) on
page 92 describes the TLB.
When data address translation is disabled (MSR[DR] = 0), the Data Cache Write-through Register (DCWR) sets
the storage attribute. Each bit in the DCWR (DCWR[W0:W31]) controls the write strategy of a 128MB storage
region (see Real-Mode Storage Attribute Control on page 105). If DCWR[Wn] = 0, write-back is enabled for the
specified region; otherwise, write-through is enabled.
Programming Note: The PowerPC Architecture does not support memory models in which write-through is
enabled and caching is inhibited.
3.4.3 DCU Load and Store Strategies
The DCU can control whether a load receives one word or one line of data from main memory. For cacheable
memory, the load without allocate (LWOA) field of the CCR0 controls the type of load resulting from a load miss. If
CCR0[LWOA] = 0, a load miss causes a line fill. If CCR0[LWOA] = 1, load misses do not result in a line fill, but in a
word load from external memory. For infrequent reads of non-contiguous memory, setting CCR0[LWOA] = 1 may
provide a small performance improvement.
For non cacheable memory and for loads misses when CCR0[LWOA] = 1, the load word as line (LWL) field in the
CCR0 affects whether load misses are satisfied with a word, or with eight words (the equivalent of a cache line) of
data. If CCR0[LWL] = 0, only the target word is bypassed to the core. If CCR0[LWL] = 1, the DCU saves eight
words (one of which is the target word) in the fill buffer and bypasses the target data to the core to satisfy the load
word request. The fill buffer is not written to the data cache array.
Setting CCR0[LWL] = 1 provides the fastest accesses to sequential non cacheable memory. Subsequent loads
from the same line are bypassed to the core from the fill buffer and do not result in additional external memory
accesses. The load data remains valid in the fill buffer until one of the following occurs: the beginning of a
subsequent load that requires the fill buffer, a store to the target address, a dcbi or dccci instruction issued to the
target address, or the execution of a
sync instruction. Non cacheable loads to guarded storage never cause a line
transfer on the PLB even if CCR0[LWL] = 1. Subsequent loads to the same non cacheable storage are always
requested again from the PLB.
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