AMCC PPC405 - 8. Debugging; 8.2 Debug Interfaces; 8.3 IEEE 1149.1 Test Access Port (JTAG Debug Port)

AMCC Proprietary 137
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
8. Debugging
The debug facilities of the PPC405 include support for debug modes for debugging during hardware and software
development, and debug events that allow developers to control the debug process. Debug registers control the
debug modes and debug events. The debug registers are accessed through software running on the processor or
through a JTAG debug port. The debug interface is the JTAG debug port. The JTAG debug port can also be used
for board test.
The debug modes, events, controls, and interface provide a powerful combination of debug facilities for a wide
range of hardware and software development tools.
8.1 Development Tool Support
The RISCWatch™ product is an example of a development tool that uses the external debug mode, debug events,
and the JTAG debug port to implement a hardware and software development tool. The RISCTrace™ feature of
RISCWatch is an example of a development tool that uses the real-time instruction trace capability of the PPC405.
8.2 Debug Interfaces
The PPC405 provides JTAG and trace interfaces to support hardware and software test and debug. Typically, the
JTAG interface connects to a debug port external to the PPC405; the debug port is typically connected to a JTAG
connector on a processor board.
The trace interface connects to a trace port, also external to the PPC405, that is typically connected to a trace
connector on the processor board.
8.3 IEEE 1149.1 Test Access Port (JTAG Debug Port)
The IEEE 1149.1 Test Access Port (TAP), commonly called the JTAG (Joint Test Action Group) debug port, is an
architectural standard described in IEEE Std 1149.1–1990,
IEEE Standard Test Access Port and Boundary
Scan Architecture
. The standard describes a method for accessing internal chip facilities using a four- or five-
signal interface.
The JTAG debug port, originally designed to support scan-based board testing, is enhanced to support the
attachment of debug tools. The enhancements, which are designed to the IEEE 1149.1 specifications for vendor-
specific extensions, are compatible with standard JTAG hardware for boundary-scan system testing.
JTAG Signals The JTAG debug port implements the four required JTAG signals: TCK,
TMS, TDI, and TDO, and the optional TRST
signal.
JTAG Clock
Requirements
The frequency of the TCK signal can range from DC to one-half of the
internal chip clock frequency.
JTAG Reset
Requirements
The JTAG debug port logic is reset at the same time as a system reset.
Upon receiving TRST
, the JTAG debug port returns to the Test-Logic Reset
state.