AMCC PPC405 - Figures

AMCC Proprietary 11
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
Figures
Figure 2-2. PPC405 Programming Model—Registers .......................................................................................34
Figure 2-1. PPC405 Programming Model—Registers .......................................................................................34
Figure 2-3. General Purpose Registers (GPR0-GPR31) ...................................................................................35
Figure 2-4. Count Register (CTR) ......................................................................................................................36
Figure 2-5. Link Register (LR) ............................................................................................................................37
Figure 2-6. Fixed Point Exception Register (XER) .............................................................................................38
Figure 2-7. Special Purpose Register General (SPRG0–SPRG7) ....................................................................39
Figure 2-8. Processor Version Register (PVR) ..................................................................................................39
Figure 2-9. Condition Register (CR) ..................................................................................................................40
Figure 2-10. PPC405 Data Types ........................................................................................................................42
Figure 2-11. Normal Word Load or Store (Big Endian Storage Region) ..............................................................48
Figure 2-12. Byte-Reverse Word Load or Store (Little Endian Storage Region) .................................................48
Figure 2-13. Byte-Reverse Word Load or Store (Big Endian Storage Region) ....................................................48
Figure 2-14. Normal Word Load or Store (Little Endian Storage Region) ...........................................................49
Figure 2-15. PPC405 Instruction Pipeline ............................................................................................................50
Figure 3-1. Instruction Flow ...............................................................................................................................70
Figure 3-2. Core Configuration Register 0 (CCR0) ............................................................................................77
Figure 3-3. Instruction Cache Debug Data Register (ICDBDR) .........................................................................80
Figure 4-1. OCM Address Usage .......................................................................................................................86
Figure 5-1. Effective-to-Real Address Translation Flow ....................................................................................92
Figure 5-2. TLB Entries ......................................................................................................................................93
Figure 5-3. ITLB/DTLB/UTLB Address Resolution ............................................................................................98
Figure 5-4. Process ID (PID) ............................................................................................................................102
Figure 5-5. Zone Protection Register (ZPR) ....................................................................................................103
Figure 5-6. Generic Storage Attribute Control Register ...................................................................................106
Figure 6-1. Machine State Register (MSR) ......................................................................................................114
Figure 6-2. Save/Restore Register 0 (SRR0) ..................................................................................................115
Figure 6-3. Save/Restore Register 1 (SRR1) ..................................................................................................115
Figure 6-4. Save/Restore Register 2 (SRR2) ..................................................................................................115
Figure 6-5. Save/Restore Register 3 (SRR3) ..................................................................................................116
Figure 6-6. Exception Vector Prefix Register (EVPR) ......................................................................................116
Figure 6-7. Exception Syndrome Register (ESR) ............................................................................................116
Figure 6-8. Data Exception Address Register (DEAR) ....................................................................................118
Figure 7-1. Relationship of Timer Facilities to the Time Base .........................................................................129
Figure 7-2. Time Base Lower (TBL) .................................................................................................................130
Figure 7-3. Time Base Upper (TBU) ................................................................................................................130
Figure 7-4. Programmable Interval Timer (PIT) ...............................................................................................132
Figure 7-5. Watchdog State Machine ..............................................................................................................133
Figure 7-6. Timer Status Register (TSR) .........................................................................................................135
Figure 7-7. Timer Control Register (TCR) ........................................................................................................136