AMCC Proprietary 353
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
10. Register Summary
Registers are grouped into categories, based on access mode: General Purpose Registers (GPRs), Special
Purpose Registers (SPRs), Time Base Registers (TBRs), the Machine State Register (MSR), the Condition
Register (CR), Device Control Registers (DCRs), and memory-mapped I/O (MMIO) registers.
This chapter provides an alphabetical listing and bit definitiions for all the registers provided by the PPC405
processor.
10.1 Reserved Registers
Any register numbers not listed in the tables which follow are reserved, and should be neither read nor written.
These reserved register numbers may be used for additional functions in future processors.
10.2 Reserved Fields
For all registers with fields marked as reserved, the reserved fields should be written as zero and read as
undefined. That is, when writing to a reserved field, write a zero to that field. When reading from a reserved field,
ignore that field.
The recommended coding practice is to perform the initial write to a register with reserved fields as described in the
preceding paragraph, and to perform all subsequent writes to the register using a read-modify-write strategy: read
the register, alter desired fields with logical instructions, and then write the register.
10.3 General Purpose Registers
The PPC405 processor core provides 32 General Purpose Registers (GPRs). The contents of these registers can
be loaded from memory using load instructions and stored to memory using store instructions. GPRs are also
addressed by all integer instructions.
10.4 Machine State Register and Condition Register
The CR and MSR are accessed by means of special instructions,and do not require addressing.
Table 10-1. PPC405 General Purpose Registers
Mnemonic Register Name
GPR Number
Access
See
Page
GPR0–GPR31 General Purpose Register 0:31 0x00–0x1F Read/Write 35
Table 10-2. PPC405 General Purpose Registers
Mnemonic Register Name
Number
Access
See
Page
CR Condition Register NA Read/Write 39
MSR Machine State Register NA Read/Write 114
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