AMCC PPC405 - DCU Operations; Table 3-2. Data Cache Organization

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AMCC Proprietary 73

Revision 1.02 - September 10, 2007

PPC405 Processor

Preliminary User’s Manual

A bypass path handles data operations in cache-inhibited memory and improves performance during line fill

operations.

3.4.1 DCU Operations

Data from cacheable memory regions are copied from external memory into lines in the data cache array so that

subsequent cache operations result in cache hits. Loads and stores that hit in the DCU are completed in one cycle.

For loads, GPRs receive the requested byte, halfword, or word of data from the data cache array. The DCU

supports byte-writeability to improve the performance of byte and halfword store operations.

Cache operations require a line fill when they require data from cacheable memory regions that are not currently in

the DCU. A line fill is the movement of a cache line (eight words) from external memory to the data cache array.

Eight words are copied from external memory into the fill buffer, either targetword-first or sequentially. Loading

order is controlled by the PLB slave. Target-word-first fills start at the requested word, continue to the end of the

line, and then wrap to fill the remaining words at the beginning of the line. Sequential fills start at the first word of

the cache line and proceed sequentially to the last word of the line. In both types of fills, the fill buffer, when full, is

transferred to the data cache array. The cache line is marked valid when it is filled.

Loads that result in a line fill, and loads from non cacheable memory, are sent to a GPR. The requested byte,

halfword, or word is sent from the DCU to the GPR from the fill buffer, using a cache bypass mechanism. Additional

loads for data in the fill buffer can be bypassed to the GPR until the data is moved into the data array.

Stores that result in a line fill have their data held in the fill buffer until the line fill completes. Additional stores to the

line being filled will also have their data placed in the fill buffer before being transferred into the data cache array.

To complete a line fill, the DCU must access the tag and data arrays. The tag array is read to determine the tag

addresses, the LRU line, and whether the LRU line is dirty. A dirty cache line is one that was accessed by a store

instruction after the line was established, and can be inconsistent with external memory. If the line being replaced

is dirty, the address and the cache line must be saved so that external memory can be updated. During the cache

line fill, the LRU bit is set to identify the line opposite the line just filled as LRU.

When a line fill completes and replaces a dirty line, a line flush begins. A flush copies updated data in the data

cache array to main storage. Cache flushes are always sequential, starting at the first word of the cache line and

proceeding sequentially to the end of the line.

Table 3-2. Data Cache Organization

Tags (Two-way Set) Data (Two-way Set)

Way A Way B Way A Way B