AMCC Proprietary 153
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
The dcbt and dcbtst instructions can cause DAC-read debug events regardless of cachability.
Although
dcbf and dcbst are architecturally “loads,” these instructions can create DAC-write (but not DAC-read)
debug events. In a debug environment, the fact that external memory is being written is the event of interest.
Even though
dcread and dccci are not address-specific (they affect a congruence class regardless of the
instruction operand address), and are considered “loads,” in the PPC405 they do not cause DAC debug events.
All ICU operations (
icbi, icbt, iccci, and icread) are architecturally treated as “loads.” icbi and icbt cause DAC
debug events.
iccci and icread do not cause DAC debug events in the PPC405.
8.8.13.4 DAC Applied to String Instructions
An
stswx instruction with a string length of 0 is a no-op. The lswx instruction with the string length equal to 0 does
not alter the RT operand with undefined data, as allowed by the PowerPC Architecture. Neither
stswx nor lswx
with zero length causes a DAC debug event because storage is not accessed by these instructions.
8.8.14 Data Value Compare Debug Event
A data value compare (DVC) debug event can occur only after execution of a load or store instruction to an
address that compares with the address in one of the DAC
n registers and has a data value that matches the
corresponding DVC
n register. Therefore, a DVC debug event requires both the data address comparison and the
data value comparison to be true. A DVCn debug event when enabled in the DBCR1 supersedes a DACn debug
event since the DVCn and the DACn both use the same DACn register.
DVC1 debug events are enabled by setting the appropriate DAC enable DBCR1[D1R,D1W] to cause an address
comparison and by setting any bit combination in the DBCR1[DV1BE]. DVC2 debug events are enabled by setting
the appropriate DAC enable DBCR1[D2R,D2W] to cause an address comparison and by setting any bit
combination in the DBCR1[DV1BE]. Each bit in DBCR1[DV1BE, DV2BE] corresponds to a byte in DVC1 and
DVC2. Exact address compare and range address compare work the same for DVC as for a simple DAC.
DBSR[DR1] and DBSR[DW1] record status for DAC1 debug events. Which DBSR bit is set depends on the setting
of DBCR1[D1R] and DBCR[D1W]. If DBCR1[D1R] = 1, DBSR[DR1] = 1, assuming that a DVC event occurred.
Similarly, if DBCR1[D1W] = 1, DBSR[DW1] = 1, assuming that a DVC event occurred.
Similarly, DBSR[DR2] and DBSR[DW2] record status for DAC2 debug events. Which DBSR bit is set depends on
the setting of DBCR1[D2R] and DBCR[D2W]. If DBCR1[D2R] = 1, DBSR[DR2] = 1, assuming that a DVC event
occurred. Similarly, if DBCR1[D2W] = 1, DBSR[DW2] = 1, assuming that a DVC event occurred.
In the following example, a DVC1 event is enabled by setting DBCR1[D1R] = 1, DBCR1[D1W] = 1, DBCR1[DA12]
= 0, and DBCR1[DV1BE] = 0000. When the data address and data value match the DAC1 and DVC1, a DVC1
event is recorded in DBSR[DR1] or DBSR[DW1], depending on whether the operation is a load (read) or a store
(write). This example corresponds to the last line of Table 8-4.
In Table 8-4 on page 154,
n is 1 or 2, depending on whether the bits apply to DAC1, DAC2, DVC1, and DVC2
events. “Hold” indicates that the DBSR holds its value unless cleared by software. “RA” indicates that the operation
is a read (load) and the data address compares (exact or range). “WA” indicates that the operation is a write (store)
and the data address compares (exact or range). “RV” indicates that the operation is a read (load), the data
address compares (exact or range), and the data value compares according to DBCR1[DVC
n].
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