AMCC Proprietary 25
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
The MMU divides logical storage into pages. Eight page sizes (1KB, 4KB, 16KB, 64KB, 256KB, 1MB, 4MB, and
16MB) are simultaneously supported, so that, at any given time, the TLB can contain entries for any combination of
page sizes. For a logical to physical translation to occur, a valid entry for the page containing the logical address
must be in the TLB. Addresses for which no TLB entry exists cause TLB-Miss exceptions.
To improve performance, 4 instruction-side and 8 data-side TLB entries are kept in shadow arrays. The shadow
arrays prevent TLB contention. Hardware manages the replacement and invalidation of shadow-TLB entries; no
system software action is required. The shadow arrays can be thought of as level 1 TLBs, with the main TLB
serving as a level 2 TLB.
When address translation is enabled, the translation mechanism provides a basic level of protection. Physical
addresses not mapped by a page entry are inaccessible when translation is enabled. Read access is implied by
the existence of the valid entry in the TLB. The EX and WR bits in the TLB entry further define levels of access for
the page, by permitting execute and write access, respectively.
The Zone Protection Register (ZPR) enables the system software to override the TLB access controls. For
example, the ZPR provides a way to deny read access to application programs. The ZPR can be used to classify
storage by type; access by type can be changed without manipulating individual TLB entries.
The PowerPC Architecture provides WIU0GE (write-back/write through, cachability, user-defined 0, guarded,
endian) storage attributes that control memory accesses, using bits in the TLB or, when address translation is
disabled, storage attribute control registers.
When address translation is enabled (MSR[IR, DR] = 1), storage attribute control bits in the TLB control the storage
attributes associated with the current page. When address translation is disabled (MSR[IR, DR] = 0), bits in each
storage attribute control register control the storage attributes associated with storage regions. Each storage
attribute control register contains 32 fields. Each field sets the associated storage attribute for a 128MB memory
region. See the topic Real-Mode Storage Attribute Control in the PPC405 Processor User’s Manual for details
about the storage attribute control registers.
1.4.3 Debug
The processor core debug facilities include debug modes for the various types of debugging used during hardware
and software development. Also included are debug events that allow developers to control the debug process.
Debug modes and debug events are controlled using debug registers in the chip. The debug registers are
accessed either through software running on the processor, or through the JTAG port. The JTAG port can also be
used for board test.
The debug modes, events, controls, and interfaces provide a powerful combination of debug facilities for hardware
and software development tools.
1.4.3.1 Development Tool Support
The PPC405 is supported by a wide range of hardware and software development tools.
An operating system debugger is an example of an operating system-aware debugger, implemented using
software traps.
1.4.3.2 Debug Modes
The internal, external, real-time-trace, and debug wait modes support a variety of debug tool used in embedded
systems development. These debug modes are described in detail in Debug Modes on page 139.
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