AMCC Proprietary 141
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
The processor enters debug wait mode when internal and external debug modes are disabled
(DBCR0[IDM, EDM] = 0), debug wait mode is enabled (MSR[DWE] = 1), debug wait is enabled by the JTAG
debugger, and a debug event occurs.
For example, while the PPC405 is in debug wait mode, an external device might generate an interrupt that requires
immediate service. The PPC405 can service the interrupt (vector to an interrupt handler and execute the interrupt
handler code) and return to the previous stopped state.
Debug wait mode relies only on internal processor resources, so it can be used to debug both system hardware
and software problems. This mode can also be used for software development on systems without a control
program, or to debug control program problems.
In this mode, access to the processor is through the JTAG debug port.
8.5.4 Real-time Trace Debug Mode
Real-time trace debug mode supports the generation of trigger events for tracing the instruction stream being
executed out of the instruction cache in real-time. In this mode, debug events can be used to control the collection
of trace information through the use of trigger event generation. The broadcast of trace information is independent
of the use of debug events as trigger events.This mode does not alter the processor performance.
A trace event occurs when internal and external debug modes are disabled (DBCR0[IDM, EDM] = 0) and a debug
events occurs.
When a trace event occurs, a trace device can capture trace signals that provide the instruction trace information.
Most trace events generated from debug events are blocked when internal debug, external debug, or debug wait
modes are enabled
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