AMCC PPC405 - Instruction Cache Cachability Register (ICCR); Storage Guarded Register (SGR); Storage Little-Endian Register (SLER); Storage User-Defined 0 Register (SU0 R)

AMCC Proprietary 107
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
After any reset, all DCCR bits are set to 0. No memory regions are cacheable. Before memory regions can be
designated as cacheable in the DCCR, it is necessary to execute the dccci instruction once for each congruence
class in the DCU cache array. This procedure invalidates all congruence classes. The DCCR can then be
reconfigured, and the DCU can begin normal operation.
The PowerPC Architecture does not support memory models in which write-through is enabled and caching is
inhibited.
5.8.1.3 Instruction Cache Cachability Register (ICCR)
The ICCR controls the I storage attribute for instruction fetches. Note that the polarity of the bits in this register is
opposite of that of the I attribute (ICCR[Sn] = 1 enables caching, while TLB_entry[I] = 1 inhibits caching).
After any reset, all ICCR bits are set to 0. No memory regions are cacheable. Before memory regions can be
designated as cacheable in the ICCR, it is necessary to execute the iccci instruction. This procedure invalidates all
congruence classes. The ICCR can then be reconfigured, and the ICU can begin normal operation.
5.8.1.4 Storage Guarded Register (SGR)
The SGR controls the G storage attribute for instruction and data accesses.
This attribute does not affect data accesses; the PPC405 does not perform speculative loads or stores.
After any reset, all SGR bits are set to 1, marking all storage as guarded. For best performance, system software
should clear the guarded attribute of appropriate regions as soon as possible. If MSR[IR] = 1, the G attribute comes
from the TLB entry. Attempting to execute from a guarded region in translate mode causes an instruction storage
interrupt. See Instruction Storage Interrupt on page 121 for more information.
5.8.1.5 Storage User-defined 0 Register (SU0R)
The Storage User-defined 0 Register (SU0R) controls the user-defined (U0) storage attribute for instruction and
data accesses.
After any reset, all SU0R bits are set to 0.
5.8.1.6 Storage Little-Endian Register (SLER)
The SLER controls the E storage attribute for instruction and data accesses.
This attribute determines the byte ordering of storage. Byte Ordering on page 44 provides a detailed description of
byte ordering in the PowerPC Embedded Environment.
After any reset, all SLER bits are set to 0 (big endian).