AMCC Proprietary 109
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
6. Interrupt Handling
An interrupt is the action in which the processor saves its old context (MSR and instruction pointer) and begins
execution at a pre-determined interrupt-handler address, with a modified MSR. Exceptions are events which, if
enabled, cause the processor to take an interrupt. Exceptions are generated by signals from internal and external
peripherals, instructions, internal timer facilities, debug events, or error conditions.
Table 6-2 on page 113 lists the interrupts handled by the PPC405 in the order of interrupt vector offsets. Detailed
descriptions of each interrupt follow, in the same order. Table 6-2 also provides an index to the descriptions.
Several registers support interrupt handling and control.General Interrupt Handling Registers on page 114
describes the general interrupt handling registers:
• Data Exception Address Register (DEAR)
• Exception Syndrome Register (ESR)
• Exception Vector Prefix Register (EVPR)
• Machine State Register (MSR)
• Save/Restore Registers (SRR0–SRR3)
6.1 Architectural Definitions and Behavior
Precise interrupts are those for which the instruction pointer saved by the interrupt must be either the address of
the excepting instruction or the address of the next sequential instruction. Imprecise interrupts are those for which
it is possible (but not required) for the saved instruction pointer to be something else, possibly prohibiting
guaranteed software recovery.
Note that “precise” and “imprecise” are defined assuming that the interrupts are unmasked (enabled to occur)
when the associated exception occurs. Consider an exception that would cause a precise interrupt, if the interrupt
was enabled at the time of the exception, but that occurs while the interrupt is masked. Some exceptions of this
type can cause the interrupt to occur later, immediately upon its enabling. In such a case, the interrupt is not
considered precise with respect to the enabling instruction, but imprecise (“delayed precise”) with respect to the
cause of the exception.
Asynchronous interrupts are caused by events which are independent of instruction execution. All asynchronous
interrupts are precise, and the following rules apply:
1. All instructions prior to the one whose address is reported to the interrupt handling routine (in the save/restore
register) have completed execution. However, some storage accesses generated by these preceding instruc-
tions may not have completed.
2. No subsequent instruction has begun execution, including the instruction whose address is reported to the
interrupt handling routine.
3. The instruction having its address reported to the interrupt handler may appear not to have begun execution, or
may have partially completed.
Synchronous interrupts are caused directly by the execution (or attempted execution) of instructions. Synchronous
interrupts can be either precise or imprecise.
For synchronous precise interrupts, the following rules apply:
1. The save/restore register addresses either the instruction causing the exception or the next sequential instruc-
tion. Which instruction is addressed is determined by the interrupt type and status bits.
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