AMCC PPC405 - 3.6 Cache Control and Debugging Features

AMCC Proprietary 77
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
3.6 Cache Control and Debugging Features
Registers and instructions are provided to control cache operation and help debug cache problems. For ICU
debug, the icread instruction and the Instruction Cache Debug Data Register (ICDBDR) are provided. See ICU
Debugging on page 80 for more information. For DCU debug, the dcread instruction is provided. See DCU
Debugging on page 81 for more information. CCR0 controls the behavior of the icread and the dcread
instructions.
dcbt
Data Cache Block Touch
Fills a block with data, if the address is cacheable and the data is not already in the
cache. If the address is non cacheable, this instruction is a no-op.
dcbtst
Data Cache Block Touch for Store
Implemented identically to the
dcbt instruction for compatibility with compilers and other
tools.
dcbz
Data Cache Block Set to Zero
Fills a line in the cache with zeros and marks the line as modified.
If the line is not currently in the cache (and the address is marked as cacheable and
non-write-through), the line is established, filled with zeros, and marked as modified
without actually filling the line from external memory. If the line is marked as either non
cacheable or write-through, an alignment exception results.
dccci
Data Cache Congruence Class Invalidate
Invalidates a congruence class (both cache ways).
This is a privileged instruction.
dcread
Data Cache Read
Reads either a data cache tag entry or a data word from a data cache line, typically for
debugging. Bits in CCR0 control instruction behavior (see Cache Control and Debugging
Features on page 77).
This is a privileged instruction.
Figure 3-2. Core Configuration Register 0 (CCR0)
0:5
Reserved
6 LWL Load Word as Line
0 The DCU performs load misses or non-
cacheable loads as words, halfwords, or bytes,
as requested
1 For load misses or non cacheable loads, the
DCU moves eight words (including the target
word) into the line fill buffer
7 LWOA Load Without Allocate
0 Load misses result in line fills
1 Load misses do not result in a line fill, but in non
cacheable loads
8 SWOA Store Without Allocate
0 Store misses result in line fills
1 Store misses do not result in line fills, but in non
cacheable stores
9 DPP1 DCU PLB Priority Bit 1
0 DCU PLB priority 0 on bit 1
1 DCU PLB priority 1 on bit 1
DCU logic dynamically controls DCU priority bit 0.