110 AMCC Proprietary
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
2. All instructions preceding the instruction causing the exception have completed execution. However, some
storage accesses generated by these preceding instructions may not have completed.
3. The instruction causing the exception may appear not to have begun execution (except for causing the excep-
tion), may have partially completed, or may have completed, depending on the interrupt type.
4. No subsequent instruction has begun execution.
Refer to PowerPC Embedded Environment for an architectural description of imprecise interrupts.
Machine check interrupts are a special case typically caused by some kind of hardware or storage subsystem
failure, or by an attempt to access an invalid address. A machine check can be indirectly caused by the execution
of an instruction, but not recognized or reported until long after the processor has executed past the instruction that
caused the machine check. As such, machine check interrupts cannot properly be thought of as synchronous, nor
as precise or imprecise. For machine checks, the following general rules apply:
1. No instruction following the one whose address is reported to the machine check handler in the save/restore
register has begun execution.
2. The instruction whose address is reported to the machine check handler in the save/restore register, and all
previous instructions, may or may not have completed successfully. All previous instructions that would ever
complete have completed, within the context existing before the machine check interrupt. No further interrupt
(other than possible additional machine checks) can occur as a result of those instructions.
6.2 Behavior of the PPC405 Implementation
All interrupts, except for machine checks, are handled precisely. Precise handling implies that the address of the
excepting instruction (for synchronous exceptions other than the system call exception), or the address of the next
instruction to be executed (asynchronous exceptions and the system call exception), is passed to an interrupt
handling routine. Precise handling also implies that all instructions that precede the instruction whose address is
reported to the interrupt handling routine have executed and that no subsequent instruction has begun execution.
The specific instruction whose address is reported may not have begun execution or may have partially completed,
as specified for each precise interrupt type.
Synchronous precise interrupts include most debug event interrupts, program interrupts, instruction and data
storage interrupts, TLB miss interrupts, system call interrupts, and alignment interrupts.
Asynchronous precise interrupts include the critical and noncritical external interrupts, and can be caused by on-
chip peripherals, timer facility interrupts, and some debug events.
In the PPC405, machine checks are handled as critical interrupts (see Critical and Noncritical Interrupts on
page 112). If a machine check is associated with an instruction fetch, the critical interrupt save/restore register
contains the address of the instruction being fetched when the machine check occurred.
The synchronism of instruction-side machine checks (errors that occur while attempting to fetch an instruction from
external memory) requires further explanation. Fetch requests to cacheable memory that miss in the instruction
cache unit (ICU) cause an instruction cache line fill (eight words). If any instructions (words) in the fetched line are
associated with an exception, an interrupt occurs upon attempted execution and the cache line is invalidated.
It is improper to declare an exception when an erroneous word is passed to the fetcher; the address could be the
result of an incorrect speculative access. It is quite likely that no attempt will be made to execute an instruction from
the erroneous address. An instruction-side machine check interrupt occurs only when execution is attempted. If an
exception occurs, execution is suppressed, SRR2 contains the erroneous address, and the indicates that an
instruction-side machine check occurred. Although such an interrupt is clearly asynchronous to the erroneous
memory access, it is handled synchronously with respect to the attempted execution from the erroneous address.
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