AMCC Proprietary 41
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
The CR[CR0]LT, GT, EQ subfields are set as the result of an algebraic comparison of the instruction result to 0,
regardless of the type of instruction that sets CR[CR0]. If the instruction result is 0, the EQ subfield is set to 1. If the
result is not 0, either LT or GT is set, depending on the value of the most significant bit of the result.
When updating CR[CR0], the most significant bit of an instruction result is considered a sign bit, even for
instructions that produce results that are not usually thought of as signed. For example, logical instructions such as
and., or., and nor. update CR[CR0]LT, GT, EQ using such an arithmetic comparison to 0, although the result of
such a logical operation is not actually an arithmetic result.
If an arithmetic overflow occurs, the “sign” of an instruction result indicated in CR[CR0]LT, GT, EQ might not
represent the “true” (infinitely precise) algebraic result of the instruction that set CR0. For example, if an add.
instruction adds two large positive numbers and the magnitude of the result cannot be represented as a twos-
complement number in a 32-bit register, an overflow occurs and CR[CR0]LT, SO are set, although the infinitely
precise result of the add is positive.
Adding the largest 32-bit twos-complement negative number, 0x8000 0000, to itself results in an arithmetic
overflow and 0x0000 0000 is recorded in the target register. CR[CR0]EQ, SO is set, indicating a result of 0, but the
infinitely precise result is negative.
The CR[CR0]SO subfield is a copy of XER[SO]. Instructions that do not alter the XER[SO] bit cannot cause an
overflow, but even for these instructions CR[CR0]SO is a copy of XER[SO].
Some instructions set CR[CR0] differently or do not specifically set any of the subfields. These instructions include:
• Compare instructions
cmp, cmpi, cmpl, cmpli
• CR logical instructions
crand, crandc, creqv, crnand, crnor, cror, crorc, crxor, mcrf
• Move CR instructions
mtcrf, mcrxr
• stwcx.
The instruction descriptions provide detailed information about how the listed instructions alter CR[CR0].
2.3.4 The Time Base
The PowerPC Architecture provides a 64-bit time base. Time Base on page 130 describes the architected time
base. Access to the time base is through two 32-bit time base registers (TBRs). The least-significant 32 bits of the
time base are read from the Time Base Lower (TBL) register and the most-significant 32 bits are read from the
Time Base Upper (TBU) register.
User-mode access to the time base is read-only, and there is no explicitly privileged read access to the time base.
The mftb instruction reads from TBL and TBU. Writing the time base is accomplished by moving the contents of a
GPR to a pair of SPRs, which are also called TBL and TBU, using mtspr.
Table 2-4 shows the mnemonics and names of the TBRs.
Table 2-4. Time Base Registers
Mnemonic Register Name Access
TBL Time Base Lower (Read-only) Read-only
TBU Time Base Upper (Read-only) Read-only
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