AMCC PPC405 - 3.6.1 CCR0 Programming Guidelines

AMCC Proprietary 79
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
3.6.1 CCR0 Programming Guidelines
Several fields in CCR0 affect ICU and DCU operation. Altering these fields while the cache units are involved in
PLB transfers can cause errant operation, including a processor hang.
To guarantee correct ICU and DCU operation, specific code sequences must be followed when altering CCR0
fields.
CCR0[IPP] and [FWOA] affect ICU operation. If these fields are altered, execution of the following code sequence
(Sequence 1) is required:
! SEQUENCE 1 Altering CCR0[IPP, FWOA]
! Turn off interrupts
mfmsr RM
addis RZ,r0,0x0002 ! CE bit
ori RZ,RZ,0x8000 ! EE bit
andc RZ,RM,RZ ! Turn off MSR[CE,EE]
mtmsr RZ
! sync
sync
! Touch code sequence into i-cache
addis RX,r0,seq1@h
ori RX,RX,seq1@l
icbt r0,RX
! Call function to alter CCR0 bits
b seq1
back:
! Restore MSR to original value
mtmsr RM
•
•
•
! The following function must be in cacheable memory
.align 5 ! Align CCR0 altering code on a cache line boundary.
seq1:
icbt r0,RX ! Repeat ICBT and execute an ISYNC to guarantee CCR0
isync ! altering code has been completely fetched across the PLB.
mfspr RN,CCR0 ! Read CCR0.
andi/ori RN,RN,0xXXXX ! Execute and/or function to change any CCR0 bits.
! Can use two instructions before having to touch
! in two cache lines.
mtspr CCR0, RN ! Update CCR0.
isync ! Refetch instructions under new processor context.
b back ! Branch back to initialization code.
CCR0[DPP1] and [U0XE] affect DCU operation. If these fields are altered, execution of the following code
sequence (Sequence 2) is required. Note that Sequence 1 includes Sequence 2, so Sequence 1 can be used to
alter any CCR0 fields.