AMCC PPC405 - 2.11.6.4 Cache Management Instructions; 2.11.7 Interrupt Control Instructions; 2.11.8 TLB Management Instructions

AMCC Proprietary 66
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
2.11.6.4 Cache Management Instructions
These instructions control the operation of the ICU and DCU. Instructions are provided to fill or invalidate
instruction cache blocks. Instructions are also provided to fill, flush, invalidate, or zero data cache blocks, where a
block is defined as a 32-byte cache line.
Table 2-23 lists the PPC405 cache management instructions.
2.11.7 Interrupt Control Instructions
mfmsr and mtmsr read and write data between the MSR and a GPR to enable and disable interrupts. wrtee and
wrteei enable and disable external interrupts.
rfi and rfci return from interrupt handlers. Table 2-24 lists the
PPC405 interrupt control instructions.
2.11.8 TLB Management Instructions
The TLB management instructions read and write entries of the TLB array in the MMU, search the TLB array for an
entry which will translate a given address, and invalidate all TLB entries. There is also an instruction for
synchronizing TLB updates with other processors, but because the PPC405 is for use in uniprocessor
environments, this instruction performs no operation.
Table 2-25 lists the TLB management instructions. In the table, the syntax [.] indicates that the instruction has a
“record” form that updates CR[CR0], and a “non-record” form.
Table 2-23. Cache Management Instructions
DCU ICU
dcba
dcbf
dcbi
dcbst
dcbt
dcbtst
dcbz
dccci
dcread
icbi
icbt
iccci
icread
Table 2-24. Interrupt Control Instructions
mfmsr
mtmsr
rfi
rfci
wrtee
wrteei