AMCC PPC405 - 5.5 TLB Management

100 AMCC Proprietary
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
• In the supervisor state
– Instruction fetch from an EA having TLB_entry[EX] = 0 and ZPR[Z
n] other than 11 or 10.
– Instruction fetch from an EA having TLB_entry[G] = 1.
See Zone Protection on page 103 for a detailed discussion of zone protection. See Instruction Storage Interrupt on
page 121 for a detailed discussion of the instruction storage interrupt.
5.4.3 Data TLB Miss Interrupt
A data TLB miss interrupt is generated if data address translation is enabled and a valid TLB entry matching the EA
and PID is not present. The interrupt applies to data access instructions and cache operations (excluding cache
touch instructions).
See Data TLB Miss Interrupt on page 127 for a detailed discussion.
5.4.4 Instruction TLB Miss Interrupt
The instruction TLB miss interrupt is generated if instruction address translation is enabled and execution is
attempted for an instruction for which a valid TLB entry matching the EA and PID for the instruction fetch is not
present.
See Instruction TLB Miss Interrupt on page 127 for a detailed discussion.
5.5 TLB Management
The processor does not imply any format for the page tables or the page table entries because there is no
hardware support for page table management. Software has complete flexibility in implementing a replacement
strategy, because software does the replacing. For example, software can “lock” TLB entries that correspond to
frequently used storage by electing to never replace them, so that those entries are never cast out of the TLB.
TLB management is performed by software with some hardware assist, consisting of:
• Storage of the missed EA in the Save/Restore Register 0 (SRR0) for an instruction-side miss, or in the Data
Exception Address Register (DEAR) for a data-side miss.
• Instructions for reading, writing, searching, and invalidating the TLB, as described briefly in the following sub-
sections. See Instruction Set on page 157 for detailed instruction descriptions.
5.5.1 TLB Search Instructions (tlbsx/tlbsx.)
tlbsx locates entries in the TLB, to find the TLB entry associated with an interrupt, or to locate candidate entries to
cast out. tlbsx searches the UTLB array for a matching entry. The EA is the value to be matched; EA =
(RA|0)+(RB).
If the TLB entry is found, its index is placed in RT26:31. RT can then serve as the source register for a tlbre or
tlbwe instruction to read or write the entry, respectively. If no match is found, the contents of RT are undefined.
tlbsx. sets the Condition Register (CR) bit CR0
EQ
. The value of CR0
EQ
depends on whether an entry is found:
CR0
EQ
= 1 if an entry is found; CR0
EQ
= 0 if no entry is found.