AMCC PPC405 - System Call Interrupt; Table 6-13. Register Settings During Program Interrupts

124 AMCC Proprietary
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
The program interrupt handler does not need to reset the ESR.
When one of the following occurs, the PPC405 does not execute the instruction, but writes the address of the
excepting instruction into SRR0:
• Attempted execution of a privileged instruction in problem state
• Attempted execution of an illegal instruction (including memory management instructions when memory man-
agement is disabled
Trap instructions can be used as a program interrupt or a debug event, or both (see Debug Events on page 147 for
information about debug events). When a trap instruction is detected as a program interrupt, the PPC405 writes the
address of the trap instruction into SRR0. See tw on page 341 and twi on page 344 (both in Instruction Set on
page 157) for a detailed discussion of the behavior of trap instructions with various interrupts enabled.
After any program interrupt, the contents of the MSR ar MSR[APA] = 0, an attempt to execute an instruction
intended for an APU causes a program interrupt if MSR[APE] = 0e written into SRR1 and the MSR bits are written
with the values shown in Table 6-13. The high-order 16 bits of the program counter are written with the contents of
the EVPR; the low-order 16 bits of the program counter are written with 0x0700. Interrupt processing begins at the
new address in the program counter.
Executing an rfi instruction restores the program counter from SRR0 and the MSR from SRR1, and execution
resumes at the address in the program counter.
6.13 System Call Interrupt
System call interrupts occur when a sc instruction is executed. The PPC405 writes the address of the instruction
following the sc into SRR0. The contents of the MSR are written into SRR1 and the MSR bits are written with the
values shown in Table 6-14. The high-order 16 bits of the program counter are then written with the contents of the
EVPR and the low-order 16 bits of the program counter are written with 0x0C00. Interrupt processing begins at the
new address in the program counter.
Executing an rfi instruction restores the program counter from SRR0 and the MSR from SRR1, and execution
resumes at the address in the program counter.
ESR[PTR] Trap Excepting instruction is a trap
Table 6-13. Register Settings during Program Interrupts
SRR0 Written with the address of the excepting instruction
SRR1 Written with the contents of the MSR
PC EVPR[0:15] || 0x0700
ESR Written with the type of program interrupt. (see Table 6-12)
MCI ← unchanged
All other bits are cleared.
Table 6-12. ESR Usage for Program Interrupts (Continued)
Bits Interrupts Cause