AMCC PPC405 - Accessing Data in Little Endian Storage Regions; Powerpc Byte-Reverse Instructions

AMCC Proprietary 47
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
If a storage region is reprogrammed from one endian format to the other, the storage region must be reloaded with
program and data structures in the appropriate endian format. If the endian format of instruction memory changes,
the ICU must be made coherent with the updates. The ICU must be invalidated and the updated instruction
memory using the new endian format must be fetched so that the proper byte ordering occurs before the new
instructions are placed in the ICU.
2.5.3.2 Accessing Data in Little Endian Storage Regions
Unlike instruction fetches from little endian storage regions, data accesses from little endian storage regions are
not byte-reversed between memory and the DCU. Data byte ordering, in memory, depends on the data type (byte,
halfword, or word) of a specific data item. It is only when moving a data item of a specific type from or to a GPR that
it becomes known what type of byte reversal is required. Therefore, byte reversal during load/store accesses is
performed between the DCU and the GPR.
When accessing data in a little endian storage region:
• For byte loads/stores, no reordering occurs.
• For halfword loads/stores, bytes are reversed within the halfword.
• For word loads/stores, bytes are reversed within the word.
Note that this applies, regardless of data alignment.
The big endian and little endian mappings of the structure s, shown in “Structure Mapping Examples” on page 44,
demonstrate how the size of an item determines its byte ordering. For example:
• The word a has its four bytes reversed within the word spanning addresses 0x00–0x03.
• The halfword e has its two bytes reversed within the halfword spanning addresses 0x1C–0x1D.
Note that the array of bytes d, where each data item is a byte, is not reversed when the big endian and little endian
mappings are compared. For example, the character 'A' is located at address 0x14 in both the big endian and little
endian mappings.
In little endian storage regions, the alignment of data is treated as it is in big endian storage regions. Unlike
PowerPC little endian mode, no special alignment exceptions occur when accessing data in little endian storage
regions.
2.5.3.3 PowerPC Byte-Reverse Instructions
For big endian storage regions, normal load/store instructions move the more significant bytes of a register to and
from the lower-numbered memory addresses. The load/store with byte-reverse instructions move the more
significant bytes of the register to and from the higher numbered memory addresses.
As Figure 2-11 through Figure 2-14 illustrate, a normal store to a big endian storage region is the same as a byte-
reverse store to a little endian storage region. Conversely, a normal store to a little endian storage region is the
same as a byte-reverse store to a big endian storage region.
Figure 2-11 illustrates the contents of a GPR and memory (starting at address 00) after a normal load/store in a big
endian storage region.