22 AMCC Proprietary
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
• Page-level access control using the translation mechanism
• Software control of page replacement strategy
• Additional control over protection using zones
• WIU0GE (write-through, cachability, compressed user-defined 0, guarded, endian) storage attribute
control for each virtual memory region
• WIMU0GE storage attribute control for thirty-two real 128MB regions
• Timer support
• 64-bit time base
• Programmable interval timer (PIT), fixed interval timer (FIT), and watchdog timers
• Synchronous external time base clock input
• Debug support
• Enhanced debug support with logical operators
• Four instruction address compares (IACs)
• Two data address compares (DACs)
• Two data value compares (DVCs)
• JTAG instruction to write to ICU
• Forward or backward instruction tracing
• Minimized interrupt latency
• Advanced power management support
• PowerPC User Instruction Set Architecture (UISA) and extensions for embedded applications
• 32-bit DCR interface
1.2 PowerPC Architecture
The PowerPC Architecture comprises three levels of standards:
• PowerPC User Instruction Set Architecture (UISA), including the base user-level instruction set, user-level
registers, programming model, data types, and addressing modes. This is referred to as Book I of the
PowerPC Architecture.
• PowerPC Virtual Environment Architecture, describing the memory model, cache model, cache control
instructions, address aliasing, and related issues. While accessible from the user level, these features are
intended to be accessed from within library routines provided by the system software. This is referred to as
Book II of the PowerPC Architecture.
• PowerPC Operating Environment Architecture, including the memory management model, supervisor-level
registers, and the exception model. These features are not accessible from the user level. This is referred to as
Book III of the PowerPC Architecture.
Book I and Book II define the instruction set and facilities available to the application programmer. Book III defines
features, such as system-level instructions, that are not directly accessible by user applications. The PowerPC
Architecture is described in The PowerPC Architecture: A Specification for a New Family of RISC Processors.
The PowerPC Architecture provides compatibility of PowerPC Book I application code across all PowerPC
implementations to help maximize the portability of applications developed for PowerPC processors. This is
accomplished through compliance with the first level of the architectural definition, the PowerPC UISA, which is
common to all PowerPC implementations.
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