AMCC PPC405 - Processor Core Interfaces; Clock and Power Management; Device Control Register Bus; Interrupts

26 AMCC Proprietary
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
1.4.4 Processor Core Interfaces
The processor core provides a range of I/O interfaces.
1.4.4.1 Processor Local Bus
The PLB-compliant interface provides separate 32-bit address and 64-bit data buses for the instruction and data
sides.
1.4.4.2 Device Control Register Bus
The Device Control Register (DCR) bus interface provides access to on-chip registers for configuration and status
of peripherals such as OCM and DMA.
These registers are accessed using the mfdcr and mtdcr instructions.
1.4.4.3 Clock and Power Management
This interface supports several methods of clock distribution and power management.
1.4.4.4 JTAG
The JTAG port is enhanced to support the attachment of a debug tool such as the RISCWatch product. Through
the JTAG test access port, a debug tool can single-step the processor and interrogate internal processor state to
facilitate software debugging. The enhancements comply with the IEEE 1149.1 specification for vendor-specific
extensions, and are therefore compatible with standard JTAG hardware for boundary-scan system testing.
1.4.4.5 Interrupts
The PPC405 provides an interface to the UIC, an on-chip interrupt controller that is logically outside the processor.
The UIC combines asynchronous interrupt inputs from on-chip and off-chip sources and presents them to the
processor core using a pair of interrupt signals: critical and non-critical.
1.4.4.6 On-Chip Memory
The on-chip memory (OCM) interface supports the implementation of instruction- and data-side memory that can
be accessed at performance levels matching the cache arrays.
1.5 Processor Programming Model
The programming model is described in detail in Programming Model on page 31.
The PowerPC instruction set and Special Purpose Registers (SPRs) provide a high degree of user control over
configuration and operation of the processor core functional units.
1.5.1 Data Types
Processor core operands are bytes, halfwords, and words. Multiple words or strings of bytes can be transferred
using the load/store multiple and load/store string instructions. Data is represented in twos complement notation or
in unsigned fixed-point format.