AMCC PPC405 - Extended Mnemonics; Processor Control Instructions; Table 2-25. TLB Management Instructions; Table 2-26. Processor Control Instructions

AMCC Proprietary 67
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
2.11.9 Processor Control Instructions
These instructions move data between the GPRs and SPRs, the CR, and DCRs in the PPC405, and provide traps,
system calls, and synchronization controls.
Table 2-26 lists the processor management instructions in the PPC405.
2.11.10 Extended Mnemonics
In addition to mnemonics for instructions supported directly by hardware, the PowerPC Architecture defines
numerous extended mnemonics.
An extended mnemonic translates directly into the mnemonic of a hardware instruction, typically with carefully
specified operands. For example, the PowerPC Architecture does not define a “shift right word immediate”
instruction, because the “rotate left word immediate then AND with mask,” (rlwinm) instruction can accomplish the
same result:
rlwinm RA,RS,32–n,n,31
However, because the required operands are not obvious, the PowerPC Architecture defines an extended
mnemonic:
srwi RA,RS,n
Extended mnemonics transfer the problem of remembering complex or frequently used operand combinations to
the assembler, and can more clearly reflect a programmer’s intentions. Thus, programs can be more readable.
Refer to the following chapter and appendixes for lists of the extended mnemonics:
• Instruction Set on page 157 lists extended mnemonics under the associated hardware instruction mnemonics.
• Instruction Summary on page 357 lists extended mnemonics alphabetically, along with the hardware instruc-
tion mnemonics.
Table B-5 in Instructions by Category on page 395 lists all extended mnemonics.
Table 2-25. TLB Management Instructions
tlbia
tlbre
tlbsx
[.]
tlbsync
tlbwe
Table 2-26. Processor Control Instructions
eieio
isync
sync
mcrxr
mfcr
mfdcr
mfspr
mtcrf
mtdcr
mtspr
sc
tw
twi