128 AMCC Proprietary
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
6.19 Debug Interrupt
Debug interrupts can be either synchronous or asynchronous. These debug events generate synchronous
interrupts: branch taken (BT), data address compare (DAC), data value compare (DVC), instruction address
compare (IAC), instruction completion (IC), and trap instruction (TIE). The exception (EXC) and unconditional
(UDE) debug events generate asynchronous interrupts. See Debug Events on page 147 for more information
about debug events.
For debug events, SRR2 is written with an address, which varies with the type of debug event, as shown in
Table 6-20.
SRR3 is written with the contents of the MSR and the MSR is written with the values shown in Table 6-21. The
high-order 16 bits of the program counter are then written with the contents of the EVPR; the low-order 16 bits of
the program counter are written with 0x2000. Interrupt processing begins at the address in the program counter.
Executing an
rfci instruction restores the program counter from SRR2 and the MSR from SRR3, and execution
resumes at the address in the program counter.
Table 6-20. SRR2 during Debug Interrupts
Debug Event Address Saved in SRR2
BT
DAC
IAC
TIE
Address of the instruction causing the event
DVC
IC
Address of the instruction
following the instruction that causing the event
EXC Interrupt vector address of the initial exception that caused the exception debug event
UDE Address of next instruction to be executed at time of UDE
Table 6-21. Register Settings during Debug Interrupts
SRR2 Written with an address as described in Table 6-20
SRR3 Written with the contents of the MSR
PC EVPR[0:15] || 0x2000
DBSR Set to indicate type of debug event.
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