AMCC Proprietary 23
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
1.3 PPC405 as a PowerPC Implementation
The PPC405 implements the PowerPC UISA, user-level registers, programming model, data types, addressing
modes, and 32-bit fixed-point operations. The PPC405 fully complies with the PowerPC UISA. The UISA 64-bit and
floating point operations are not implemented. The floating point operations, which cause exceptions, can then be
emulated by software.
Most of the features of the PPC405 processor core are compatible with the PowerPC Virtual Environment and
Operating Environment Architectures. The PPC405 processor core also provides a number of optimizations and
extensions to these layers of the PowerPC Architecture. The full architecture of the PPC405 is defined by the
PowerPC Embedded Environment and the PowerPC User Instruction Set Architecture.
The primary extensions of the PowerPC Architecture defined in the Embedded Environment are:
• A simplified memory management mechanism with enhancements for embedded applications
• An enhanced, dual-level interrupt structure
• An architected DCR address space for integrated peripheral control
• The addition of several instructions to support these modified and extended resources
Some of the specific implementation features of the PPC405 are beyond the scope of the PowerPC Architecture.
These features are included to enhance performance, integrate functionality, and reduce system complexity in
embedded control applications.
1.4 RISC Processor Core Organization
The processor core consists of a 5-stage pipeline, separate instruction and data cache units, virtual memory
management unit (MMU), debug, and interfaces to other functions.
1.4.1 Instruction and Data Cache Controllers
The PPC405 processor core uses a 16-KB instruction cache unit (ICU) and an 16-KB data cache unit (DCU) to
enable concurrent accesses and minimize pipeline stalls. Both cache units are two-way set-associative and use a
32-byte line size. The instruction set provides a rich assortment of cache control instructions, including instructions
to read tag information and data arrays. See Chapter 4, “Cache Operations,” for detailed information about the ICU
and DCU.
1.4.1.1 Instruction Cache Unit
The ICU provides one or two instructions per cycle to the execution unit (EXU) over a 64-bit bus. A line buffer (built
into the output of the array for manufacturing test) enables the ICU to be accessed only once for every four
instructions, to reduce power consumption by the array.
The ICU can forward any or all of the words of a line fill to the EXU to minimize pipeline stalls caused by cache
misses. The ICU aborts speculative fetches abandoned by the EXU, eliminating unnecessary line fills and enabling
the ICU to handle the next EXU fetch. Aborting abandoned requests also eliminates unnecessary PLB activity to
increase PLB availability for other on-chip cores, such as the DMA controller.
1.4.1.2 Data Cache Unit
The DCU transfers 1, 2, 3, 4, or 8 bytes per cycle, depending on the number of byte enables presented by the
CPU. The DCU contains a single-element command and store data queue to reduce pipeline stalls; this queue
enables the DCU to independently process load/store and cache control instructions. Dynamic PLB request
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