AMCC Proprietary 58
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
When the SPR number is considered as a binary number (0b0000011010), the most-significant bit is 0. However,
the machine code for the instruction reverses the subfields, resulting in the following SPRF field: 0b1101000000.
The most-significant bit is 1; SRR0 is privileged.
When an SPR number is considered as a hexadecimal number, the second digit of the three-digit hexadecimal
number indicates whether an SPR is privileged. If the second digit is odd (1, 3, 5, 7, 9, B, D, F), the SPR is
privileged.
For example, the SPR number of SRR0 is 26 (0x01A). The second hexadecimal digit is odd; SRR0 is privileged. In
contrast, the LR is SPR 8 (0x008); the second hexadecimal digit is not odd; the LR is non-privileged.
2.9.4 Privileged DCRs
The mtdcr and mfdcr instructions themselves are privileged, in all cases. All DCRs are privileged.
2.10 Synchronization
The PPC405 supports the synchronization operations of the PowerPC Book-E architecture. There are three kinds
of synchronization defined by the architecture, each of which is described in the following sections.
2.10.1 Context Synchronization
The context of a program is the environment in which the program executes. For example, the mode (user or
supervisor) is part of the context, as are the address translation space and storage attributes of the memory pages
being accessed by the program. Context is controlled by the contents of certain registers and other resources,
such as the MSR and the translation lookaside buffer (TLB).
Under certain circumstances, it is necessary for the hardware or software to force the synchronization of a
program’s context. Context synchronizing operations include all interrupts except Machine Check, as well as the
isync, sc, rfi, and rfci instructions. Context synchronizing operations satisfy the following requirements:
1. The operation is not initiated until all instructions preceding the operation have completed to the point at which
they have reported any and all exceptions that they will cause.
2. All instructions preceding the operation must complete in the context in which they were initiated. That is, they
must not be affected by any context changes caused by the context synchronizing operation, or any instruc-
tions after the context synchronizing operation.
3. If the operation is the sc instruction (which causes a System Call interrupt) or is itself an interrupt, then the
operation is not initiated until no higher priority interrupt is pending (see Interrupt Handling on page 109).
4. All instructions that follow the operation must be re-fetched and executed in the context that is established by
the completion of the context synchronizing operation and all of the instructions which preceded it.
Note that context synchronizing operations do not force the completion of storage accesses, nor do they enforce
any ordering amongst accesses before and/or after the context synchronizing operation. If such behavior is
required, then a storage synchronizing instruction must be used (see Storage Ordering and Synchronization on
page 60).
Also note that architecturally Machine Check interrupts are not context synchronizing. Therefore, an instruction that
precedes a context synchronizing operation can cause a Machine Check interrupt after the context synchronizing
operation occurs and additional instructions have completed. For the PPC405, this can only occur with Data
Machine Check exceptions, and not Instruction Machine Check exceptions.
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