AMCC PPC405 - 5.4 TLB-Related Interrupts

AMCC Proprietary 99
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
5.4 TLB-Related Interrupts
The processor relies on interrupt handling software to implement paged virtual memory, and to enforce protection
of specified memory pages.
When an interrupt occurs, the processor clears MSR[IR, DR]. Therefore, at the start of all interrupt handlers, the
processor operates in real mode for instruction accesses and data accesses. Note that when address translation is
disabled for an instruction fetch or load/store, the EA is equal to the real address and is passed directly to the
memory subsystem (including cache units). Such untranslated addresses bypass all memory protection checks
that would otherwise be performed by the MMU.
When translation is enabled, MMU accesses can result in the following interrupts:
• Data storage interrupt
• Instruction storage interrupt
• Data TLB miss interrupt
• Instruction TLB miss interrupt
5.4.1 Data Storage Interrupt
A data storage interrupt is generated when data address translation is active, and the desired access to the EA is
not permitted for one of the following reasons:
• In the problem state
– icbi, load/store, dcbz, or dcbf with an EA whose zone field is set to no access (ZPR[Zn] = 00). In this
case, dcbt and dcbtst no-op, rather than cause an interrupt. Privileged instructions cannot cause data
storage interrupts.
– Stores, or
dcbz, to an EA having TLB[WR] = 0 (write access disabled) and ZPR[Zn] ≠ 11. (The privileged
instructions
dcbi and dccci are treated as “stores”, but cause program interrupts, rather than data storage
interrupts.)
• In supervisor state
– Data store,
dcbi, dcbz, or dccci to an EA having TLB[WR] = 0 and ZPR[Zn] other than 11 or 10.
dcba does not cause data storage exceptions (cache line locking or protection). If conditions occur that would
otherwise cause such an exception,
dcba is treated as a no-op.
Zone Protection on page 103 describes zone protection in detail. See Data Storage Interrupt on page 120 for a
detailed discussion of the data storage interrupt.
5.4.2 Instruction Storage Interrupt
An instruction storage interrupt is generated when instruction address translation is active and the processor
attempts to execute an instruction at an EA for which fetch access is not permitted, for any of the following reasons:
• In the problem state
– Instruction fetch from an EA with ZPR[Z
n]=00.
– Instruction fetch from an EA having TLB_entry[EX] = 0 and ZPR[Z
n] ≠ 11.
– Instruction fetch from an EA having TLB_entry[G] = 1.