AMCC PPC405 - Instructions in the Powerpc Embedded Environment

398 AMCC Proprietary
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
B.2 Instructions in the PowerPC Embedded Environment
To meet the functional requirements of processors for embedded systems and real-time applications, the PowerPC
Embedded Environment defines instructions that are not part of the PowerPC Architecture.
Table B-3 summarizes the PPC405 instructions in the PowerPC Embedded Environment.
nmachhw
RT, RA, RB nprod
0:31
← –((RA)
0:15
x (RB)
0:15
) signed
temp
0:32
← nprod
0:31
+ (RT)
(RT) ← temp
1:32
288
nmachhw.
CR[CR0]
nmachhwo
XER[SO, OV]
nmachhwo.
CR[CR0]
XER[SO, OV]
nmachhws
RT, RA, RB nprod
0:31
← –((RA)
0:15
x (RB)
0:15
) signed
temp
0:32
← nprod
0:31
+ (RT)
if ((nprod
0
= RT
0
) ∧ (RT
0
≠ temp
1
)) then
(RT)
← (RT
0
||
31
(¬RT
0
))
else (RT) ← temp
1:32
289
nmachhws.
CR[CR0]
nmachhwso
XER[SO, OV]
nmachhwso.
CR[CR0]
XER[SO, OV]
nmaclhw
RT, RA, RB nprod
0:31
← –((RA)
16:31
x (RB)
16:31
) signed
temp
0:32
← nprod
0:31
+ (RT)
(RT)
← temp
1:32
290
nmaclhw.
CR[CR0]
nmaclhwo
XER[SO, OV]
nmaclhwo.
CR[CR0]
XER[SO, OV]
nmaclhws
RT, RA, RB nprod
0:31
← –((RA)
16:31
x (RB)
16:31
) signed
temp
0:32
← nprod
0:31
+ (RT)
if ((nprod
0
= RT
0
) ∧ (RT
0
≠ temp
1
)) then
(RT) ← (RT
0
||
31
(¬RT
0
))
else (RT)
← temp
1:32
291
nmaclhws.
CR[CR0]
nmaclhwso
XER[SO, OV]
nmaclhwso.
CR[CR0]
XER[SO, OV]
Table B-3. Instructions in the IBM PowerPC Embedded Environment
Mnemonic Operands Function
Other Registers
Changed
Page
dcba RA, RB Speculatively establish the data cache block which contains the EA
(RA|0) + (RB).
201
dcbf RA, RB Flush (store, then invalidate) the data cache block which contains
the EA (RA|0) + (RB).
203
dcbi RA, RB Invalidate the data cache block which contains the EA
(RA|0) + (RB).
204
dcbst RA, RB Store the data cache block which contains the EA (RA|0) + (RB). 205
dcbt RA, RB Load the data cache block which contains the EA (RA|0) + (RB). 206
dcbtst RA,RB Load the data cache block which contains the EA (RA|0) + (RB). 207
Table B-2. Implementation-specific Instructions (Continued)
Mnemonic Operands Function
Other Registers
Changed
Page