AMCC Proprietary 357
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
Appendix A. Instruction Summary
This appendix contains PPC405 instructions summarized alphabetically and by opcode.
Appendix A.1 on page 357, illustrates the PPC405 instruction forms (allowed arrangements of fields within
instructions).
Appendix A.2 on page 362 lists all PPC405 mnemonics, including extended mnemonics, alphabetically. A short
functional description is included for each mnemonic.
Appendix A.3 on page 388, lists all PPC405 instructions, sorted by primary and secondary opcodes. Extended
mnemonics are not included in the opcode list.
A.1 Instruction Formats
Instructions are four bytes long. Instruction addresses are always word-aligned.
Instruction bits 0 through 5 always contain the primary opcode. Many instructions have an extended opcode in
another field. Remaining instruction bits contain additional fields. All instruction fields belong to one of the following
categories:
•Defined
These instructions contain values, such as opcodes, that cannot be altered. The instruction format diagrams
specify the values of defined fields.
•Variable
These fields contain operands, such as GPR selectors and immediate values, that can vary from execution to
execution. The instruction format diagrams specify the operands in the variable fields.
• Reserved
Bits in reserved fields should be set to 0. In the instruction format diagrams, /, //, or /// indicate reserved fields.
If any bit in a defined field does not contain the expected value, the instruction is illegal and an illegal instruction
exception occurs. If any bit in a reserved field does not contain 0, the instruction form is invalid; its result is
architecturally undefined. The PPC405 executes all invalid instruction forms without causing an illegal instruction
exception.
A.1.1 Instruction Fields
PPC405 instructions contain various combinations of the following fields, as indicated in the instruction format
diagrams that follow the field definitions. Numbers, enclosed in parentheses, that follow the field names indicate bit
positions; bit fields are indicated by starting and stopping bit positions separated by colons.
AA (30) Absolute address bit.
0 The immediate field represents an address relative to the current instruction address (CIA).
The effective address (EA) of the branch is either the sum of the LI field sign-extended to 32
bits and the branch instruction address, or the sum of the BD field sign-extended to 32 bits and
the branch instruction address.
1 The immediate field represents an absolute address. The EA of the branch is either the LI field
or the BD field, sign-extended to 32 bits.
BA (11:15) Specifies a bit in the CR used as a source of a CR-logical instruction.
BB (16:20) Specifies a bit in the CR used as a source of a CR-logical instruction.
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