358 AMCC Proprietary
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
BD (16:29) An immediate field specifying a 14-bit signed twos complement branch displacement. This field is
concatenated on the right with 0b00 and sign-extended to 32 bits.
BF (6:8) Specifies a field in the CR used as a target in a compare or mcrf instruction.
BFA (11:13) Specifies a field in the CR used as a source in a mcrf instruction.
BI (11:15) Specifies a bit in the CR used as a source for the condition of a conditional branch instruction.
BO (6:10) Specifies options for conditional branch instructions. See BO Field on Conditional Branches on
page 51.
BT (6:10) Specifies a bit in the CR used as a target as the result of a CR-Logical instruction.
D (16:31) Specifies a 16-bit signed twos-complement integer displacement for load/store instructions.
DCRN (11:20) Specifies a device control register (DCR).
FXM (12:19) Field mask used to identify CR fields to be updated by the mtcrf instruction.
IM (16:31) An immediate field used to specify a 16-bit value (either signed integer or unsigned).
LI (6:29) An immediate field specifying a 24-bit signed twos complement branch displacement; this field is
concatenated on the right with b'00' and sign-extended to 32 bits.
LK (31) Link bit.
0 Do not update the link register (LR).
1 Update the LR with the address of the next instruction.
MB (21:25) Mask begin.
Used in rotate-and-mask instructions to specify the beginning bit of a mask.
ME (26:30) Mask end.
Used in rotate-and-mask instructions to specify the ending bit of a mask.
NB (16:20) Specifies the number of bytes to move in an immediate string load or store.
OPCD (0:5) Primary opcode. Primary opcodes, in decimal, appear in the instruction format diagrams
presented with individual instructions. The OPCD field name does not appear in instruction
descriptions.
OE (21) Enables setting the OV and SO fields in the fixed-point exception register (XER) for extended
arithmetic.
RA (11:15) A GPR used as a source or target.
RB (16:20) A GPR used as a source.
Rc (31) Record bit.
0 Do not set the CR.
1 Set the CR to reflect the result of an operation.
See Condition Register (CR) on page 39 for a further discussion of how the CR bits are set.
RS (6:10) A GPR used as a source.
RT (6:10) A GPR used as a target.
SH (16:20) Specifies a shift amount.
SPRF (11:20) Specifies a special purpose register (SPR).
TO (6:10) Specifies the conditions on which to trap, as described under tw and twi instructions.
XO (21:30) Extended opcode for instructions without an OE field. Extended opcodes, in decimal, appear in the
instruction format diagrams presented with individual instructions. The XO field name does not
appear in instruction descriptions.
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