AMCC PPC405 - Processor Register Set Summary; Condition Register; Device Control Registers; General Purpose Registers

AMCC Proprietary 27
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
The address of a multibyte operand is always the lowest memory address occupied by that operand. Byte ordering
can be selected as big endian (the lowest memory address of an operand contains its most significant byte) or as
little endian (the lowest memory address of an operand contains its least significant byte).
1.5.2 Processor Register Set Summary
The processor core registers can be grouped into basic categories based on function and access mode: General
Purpose Registers (GPRs), Special Purpose Registers (SPRs), the Machine State Register (MSR), the Condition
Register (CR), and Device Control Registers (DCRs).
Register Summary on page 353 provides lists of all registers provided by the processor..
1.5.2.1 General Purpose Registers
The processor core contains 32 GPRs; each register contains 32 bits. The contents of the GPRs can be
transferred from memory using load instructions and stored to memory using store instructions. GPRs, which are
specified as operands in many instructions, can also receive instruction results and the contents of other registers.
1.5.2.2 Special Purpose Registers
Special Purpose Registers (SPRs), which are part of the PowerPC Architecture, are accessed using the mtspr and
mfspr instructions. SPRs control the use of the debug facilities, timers, interrupts, storage control attributes, and
other architected processor resources.
All SPRs are privileged (unavailable to user-mode programs), except the Count Register (CTR), the Link Register
(LR), SPR General Purpose Registers (SPRG4–SPRG7, read-only), and the Fixed Point Exception Register
(XER). Note that access to the Time Base Lower (TBL) and Time Base Upper (TBU) registers, when addressed as
SPRs, is write-only and privileged. However, when addressed as Time Base Registers (TBRs), read access to
these registers is not privileged. See The Time Base on page 41 for more information.
1.5.2.3 Machine State Register
The PPC405 processor core contains a 32-bit Machine State Register (MSR). The contents of a GPR can be
written to the MSR using the mtmsr instruction, and the MSR contents can be read into a GPR using the mfmsr
instruction. The MSR contains fields that control the operation of the processor core.
1.5.2.4 Condition Register
The PPC405 processor core contains a 32-bit Condition Register (CR). These bits are grouped into eight 4-bit
fields, CR[CR0]–CR[CR7]. Instructions are provided to perform logical operations on CR fields and bits within fields
and to test CR bits within fields. The CR fields, which are set by compare instructions, can be used to control
branches. CR[CR0] can be set implicitly by arithmetic instructions.
1.5.2.5 Device Control Registers
DCRs, which are architecturally outside of the processor core, are accessed using the mtdcr and mfdcr
instructions. DCRs are used to control, configure, and hold status for various functional units that are not part of the
processor core.
The mtdcr and mfdcr instructions are privileged, for all DCRs. Therefore, all accesses to DCRs are privileged.
See User and Supervisor Modes on page 56 for details.