AMCC PPC405 - B.13 TLB Management Instructions

AMCC Proprietary 428
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
B.13 TLB Management Instructions
The TLB management instructions read and write entries of the TLB array in the MMU, search the TLB array for an
entry which will translate a given address, invalidate all TLB entries, and synchronize TLB updates with other
processors.
rfi Return from interrupt.
(PC) ← (SRR0).
(MSR)
← (SRR1).
298
wrtee RS Write value of RS
16
to the External Enable bit (MSR[EE]). 347
wrteei E Write value of E to the External Enable bit (MSR[EE]). 348
Table B-14. TLB Management Instructions
Mnemonic Operands Function
Other Registers
Changed
Page
tlbia All of the entries in the TLB are invalidated and become unavailable
for translation by clearing the valid (V) bit in the TLBHI portion of
each TLB entry. The rest of the fields in the TLB entries are
unmodified.
334
tlbre RT, RA,WS If WS = 0:
Load TLBHI portion of the selected TLB entry into RT.
Load the PID register with the contents of the TID field of the
selected TLB entry.
(RT)
← TLBHI[(RA)]
(PID) ← TLB[(RA)]
TID
If WS = 1:
Load TLBLO portion of the selected TLB entry into RT.
(RT)
← TLBLO[(RA)]
335
tlbsx RT,RA,RB Search the TLB array for a valid entry which translates the EA
EA = (RA|0) + (RB).
If found,
(RT)
← Index of TLB entry.
If not found,
(RT) Undefined.
337
tlbsx. If found,
(RT)
← Index of TLB entry.
CR[CR0]
EQ
← 1.
If not found,
(RT) Undefined.
CR[CR0]
EQ
← 1.
CR[CR0]
LT,GT,SO
tlbsync tlbsync does not complete until all previous TLB-update instructions
executed by this processor have been received and completed by all
other processors.
For the PPC405, tlbsync is a no-op.
338
tlbwe RS, RA,WS If WS = 0:
Write TLBHI portion of the selected TLB entry from RS.
Write the TID field of the selected TLB entry from the PID register.
TLBHI[(RA)]
← (RS)
TLB[(RA)]
TID
← (PID)
24:31
If WS = 1:
Write TLBLO portion of the selected TLB entry from RS.
TLBLO[(RA)]
← (RS)
339
Table B-13. Interrupt Control Instructions (Continued)
Mnemonic Operands Function
Other Registers
Changed
Page