AMCC PPC405 - Figure 2-5. Link Register (LR); Fixed Point Exception Register (XER); Link Register (LR)

AMCC Proprietary 37
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
2.3.2.2 Link Register (LR)
The LR is written from a GPR using mtspr, and by branch instructions that have the LK bit set to 1. Such branch
instructions load the LR with the address of the instruction following the branch instruction. Thus, the LR contents
can be used as the return address for a subroutine that was called using the branch.
The LR contents can be used as a target address for the bclr instruction. This allows branching to any address.
When the LR contents represent an instruction address, LR30:31 are assumed to be 0, because all instructions
must be word-aligned. However, when LR is read using mfspr, all 32 bits are returned as written.
The LR is in the user programming model.
2.3.2.3 Fixed Point Exception Register (XER)
The XER records overflow and carry conditions generated by integer arithmetic instructions.
The Summary Overflow (SO) field is set to 1 when instructions cause the Overflow (OV) field to be set to 1. The SO
field does not necessarily indicate that an overflow occurred on the most recent arithmetic operation, but that an
overflow occurred since the last clearing of XER[SO]. mtspr(XER) sets XER[SO, OV] to the value of bit positions 0
and 1 in the source register, respectively.
Once set, XER[SO] is not reset until an mtspr(XER) is executed with data that explicitly puts a 0 in the SO bit, or
until an mcrxr instruction is executed.
XER[OV] is set to indicate whether an instruction that updates XER[OV] produces a result that “overflows” the 32-
bit target register. XER[OV] = 1 indicates overflow. For arithmetic operations, this occurs when an operation has a
carry-in to the most-significant bit of the result that does not equal the carry-out of the most-significant bit (that is,
the exclusive-or of the carry-in and the carry-out is 1).
The following instructions set XER[OV] differently. The specific behavior is indicated in the instruction descriptions
in Chapter 24, “Instruction Set.”
• Move instructions:
mcrxr, mtspr(XER)
• Multiply and divide instructions:
mullwo, mullwo., divwo, divwo., divwuo, divwuo
The Carry (CA) field is set to indicate whether an instruction that updates XER[CA] produces a result that has a
carry-out of the most-significant bit. XER[CA] = 1 indicates a carry.
The following instructions set XER[CA] differently.The specific behavior is indicated in the instruction descriptions
in Chapter 24, “Instruction Set.”
• Move instructions
mcrxr, mtspr(XER)
• • Shift-algebraic operations
sraw, srawi
Figure 2-5. Link Register (LR)
0:31 Link Register contents
If (LR) represents an instruction address, LR
30:31
should be 0.