AMCC PPC405 - 3. Cache Operations; 3.1 ICU Features; 3.2 DCU Features; 3.3 ICU Organization

AMCC Proprietary 69
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
3. Cache Operations
The PPC405 incorporates two internal caches, a 16-KB instruction cache and a 16-KB data cache. Instructions
and data can be accessed in the caches much faster than in main memory.
The instruction cache unit (ICU) controls instruction accesses to main memory and stores frequently used
instructions to reduce the overhead of instruction transfers between the instruction pipeline and external memory.
Using the instruction cache minimizes access latency for frequently executed instructions.
The data cache unit (DCU) controls data accesses to main memory and stores frequently used data to reduce the
overhead of data transfers between the GPRs and external memory. Using the data cache minimizes access
latency for frequently used data.
3.1 ICU Features
• Programmable address pipelining and prefetching for cache misses and non cacheable lines
• Support for non-cacheable hits from lines contained in the line fill buffer
• Programmable non cacheable requests to memory as 4 or 8 words (or half line or line)
• Bypass path for critical words
• Non-blocking cache for hits during fills
• Flash invalidate (one instruction invalidates entire cache)
• Programmable allocation for fetch fills, enabling program control of cache contents using the icbt instruction
• Virtually indexed, physically tagged cache arrays
• Support for 64- and 32-bit PLB slaves
• A rich set of cache control instructions
3.2 DCU Features
• Address pipelining for line fills
• Support for load hits from non cacheable and non-allocated lines contained in the line fill buffer
• Bypass path for critical words
• Non-blocking cache for hits during fills
• Write-back and write-through write strategies controlled by storage attributes
• Programmable non cacheable load requests to memory as lines or words.
• Handling of up to two pending line flushes.
• Holding of up to three stores before stalling the core pipeline
• Physically indexed, physically tagged cache arrays
• Support for 64- and 32-bit PLB slaves
• A rich set of cache control instructions
ICU Organization on page 69 and DCU Organization on page 72 describe the organization and provide overviews
of the ICU and the DCU.
3.3 ICU Organization
The ICU manages instruction transfers between external cacheable memory and the instruction queue in the
execution unit.
The ICU contains a two-way set-associative 16-KB cache memory. Each way is organized in 256 lines of eight
words (eight instructions) each.