AMCC PPC405 - Tables

AMCC Proprietary 13
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
Tables
Table 2-1. PPC405 SPRs .................................................................................................................................36
Table 2-2. XER[CA] Updating Instructions .......................................................................................................38
Table 2-3. XER[SO,OV] Updating Instructions .................................................................................................38
Table 2-4. Time Base Registers .......................................................................................................................41
Table 2-5. Alignment Exception Summary .......................................................................................................43
Table 2-6. Big Endian Mapping ........................................................................................................................46
Table 2-7. Little Endian Mapping ......................................................................................................................46
Table 2-8. Bits of the BO Field ..........................................................................................................................51
Table 2-9. Conditional Branch BO Field ...........................................................................................................52
Table 2-10. Example Memory Mapping ..............................................................................................................55
Table 2-11. Privileged Instructions .....................................................................................................................57
Table 2-12. PPC405 Instruction Set Summary ...................................................................................................61
Table 2-13. Implementation-specific Instructions ...............................................................................................62
Table 2-14. Storage Reference Instructions .......................................................................................................62
Table 2-15. Arithmetic Instructions .....................................................................................................................63
Table 2-16. Multiply-Accumulate and Multiply Halfword Instructions ..................................................................63
Table 2-17. Logical Instructions ..........................................................................................................................64
Table 2-18. Compare Instructions ......................................................................................................................64
Table 2-19. Branch Instructions ..........................................................................................................................64
Table 2-20. CR Logical Instructions ....................................................................................................................65
Table 2-21. Rotate Instructions ...........................................................................................................................65
Table 2-22. Shift Instructions ..............................................................................................................................65
Table 2-23. Cache Management Instructions .....................................................................................................66
Table 2-24. Interrupt Control Instructions ...........................................................................................................66
Table 2-25. TLB Management Instructions .........................................................................................................67
Table 2-26. Processor Control Instructions ........................................................................................................67
Table 3-1. Instruction Cache Organization .......................................................................................................70
Table 3-2. Data Cache Organization ................................................................................................................73
Table 3-3. Priority Changes With Different Data Cache Operations .................................................................82
Table 4-1. Examples of Store Data Bypass .....................................................................................................87
Table 5-1. TLB Fields Related to Page Size .....................................................................................................94
Table 5-2. Protection Applied to Cache Control Instructions ..........................................................................104
Table 6-1. Interrupt Handling Priorities ...........................................................................................................111
Table 6-2. Interrupt Vector Offsets .................................................................................................................113
Table 6-3. ESR Alteration by Various Interrupts .............................................................................................117
Table 6-4. Register Settings during Critical Input Interrupts ...........................................................................118
Table 6-5. Register Settings during Machine Check—Instruction Interrupts ..................................................119
Table 6-6. Register Settings during Machine Check—Data Interrupts ...........................................................120
Table 6-7. Register Settings during Data Storage Interrupts ..........................................................................121
Table 6-8. Register Settings during Instruction Storage Interrupts .................................................................122