AMCC PPC405 - Page 12

12 AMCC Proprietary
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
Figure 8-1. Debug Control Register 0 (DBCR0) ...............................................................................................143
Figure 8-2. Debug Control Register 1 (DBCR1) ...............................................................................................144
Figure 8-3. Debug Status Register (DBSR) .....................................................................................................145
Figure 8-4. Instruction Address Compare Registers (IAC1–IAC4) ...................................................................147
Figure 8-5. Data Address Compare Registers (DAC1–DAC2) .........................................................................147
Figure 8-6. Data Value Compare Registers (DVC1–DVC2) .............................................................................147
Figure 8-7. Inclusive IAC Range Address Compares .......................................................................................150
Figure 8-8. Exclusive IAC Range Address Compares .....................................................................................150
Figure 8-9. Inclusive DAC Range Address Compares .....................................................................................151
Figure 8-10. Exclusive DAC Range Address Compares ....................................................................................152